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HEF4543B Datasheet(PDF) 8 Page - NXP Semiconductors |
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HEF4543B Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 16 page  HEF4543B_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 27 October 2009 8 of 16 NXP Semiconductors HEF4543B BCD to 7-segment latch/decoder/driver [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). 12. Waveforms th hold time Dn to LE; see Figure 6 5 V 0 −15 - ns 10 V 15 0 - ns 15 V 20 5 - ns tW pulse width pin LE HIGH; minimum width; see Figure 6 5 V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; For test circuit see Figure 7;unless otherwise specified. Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter VDD Typical formula for PD (µW) where: PD dynamic power dissipation 5 V PD = 2200 × fi + Σ(fo × CL) × VDD2 fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, Σ(CL × fo) = sum of the outputs. 10 V PD = 10400 × fi + Σ(fo × CL) × VDD2 15 V PD = 33000 × fi + Σ(fo × CL) × VDD2 Conditions: D3 = LOW and D0 = D1 =HIGH. Fig 5. Propagation delays and output transitions times 001aaj496 VI VI VM tPHL tPLH tPHL tPHL tPHL tTLH tTHL tPLH tPLH tPLH VM VM VM VM VSS VI VSS VOH VOL VSS VI VSS LT BL Qg LE 90 % 10 % D2 |
Similar Part No. - HEF4543B_09 |
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