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MAX6909EO33 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX6909EO33 Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 33 page I2C-Compatible Real-Time Clocks with µP Supervisor and NV RAM Controller 6 _______________________________________________________________________________________ AC ELECTRICAL CHARACTERISTICS (VCC(MIN) < VCC < VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2-WIRE BUS TIMING SCL Clock Frequency fSCL (Note 9) 0.32 400.00 kHz Bus Timeout tTIMEOUT 12 s Bus Free Time Between STOP and START Condition tBUF 1.3 µs Hold Time After (Repeated) START Condition; After This Period, the First Clock Is Generated tHD:STA 0.6 µs Repeated START Condition Setup Time tSU:STA 0.6 µs STOP Condition Setup Time tSU:STO 0.6 µs Data Hold Time tHD:DAT (Notes 10, 11) 0 0.9 µs Data Setup Time tSU:DAT 100 ns SCL Low to Data Out Valid tVD:DAT (Note 8) 50 ns SCL Low Period tLOW 1.3 µs SCL High Period tHIGH 0.6 µs SCL/SDA Rise Time tR (Note 12) 20 + 0.1 x CB 300 ns SCL/SDA Fall Time (Receiving) tF (Notes 12, 13) 20 + 0.1 x CB 300 ns SCL/SDA Fall Time (Transmitting) tF (Notes 12, 13) 20 + 0.1 x CB 250 ns Pulse Width of Spike Suppressed tSP (Note 8) 50 ns Capacitive Load of Each Bus Line CB 400 pF Note 1: VRST is the reset threshold for VCC. See the Ordering Information. Note 2: All parameters are 100% tested at TA = +85°C. Limits over temperature are guaranteed by design and not production tested. Note 3: 2-wire serial interface is operational for VCC > VRST. Note 4: See the Detailed Description section (BATT function). Note 5: IBATT and ICCS are specified with SDA and SCLK pulled high, OUT floating, and CE OUT floating. Note 6: 2-wire serial interface operating at 400kHz, SDA pulled high. Note 7: For OUT switch over to BATT, VCC must fall below VRST and VBATT. For OUT switchover to VCC, VCC must be above VRST or above VBATT. Note 8: Guaranteed by design. Not production tested. Note 9: Due to the 2-wire bus timeout feature, there is a minimum specification on the SCL clock frequency based on a 31-byte burst-mode transaction to RAM. See the Timeout Feature section. Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 12: CB = total capacitance of one bus line in pF. Note 13: The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tF. |
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