Supervisor and NV RAM Controller

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9

Detailed Description

The MAX6909/MAX6910 contain eight 8-bit timekeeping

registers, two burst address registers, a trickle charge

register, a control register, a configuration register, an

alarm configuration register, and seven alarm threshold

registers, all controlled through a 2-wire serial interface.

Figure 1 is the MAX6909/MAX6910 block diagram.

The OUT pin supplies voltage for CMOS RAM or other

ICs requiring the use of backup battery power. When

BATT can act as a backup supply from either a battery

or SuperCap™. When operating from BATT, the battery-

on output (BATT ON) is pulled low and can be used as

an indicator of operation in battery backup mode.

There are two reset outputs, RESET and RESET. They

threshold, or a WDI pulse is not received when the

watchdog function is enabled. Reset thresholds are

available for 3V and 3.3V applications. See the Ordering

Information for specifics. MR is internally pulled high and

contains debounce circuitry to accommodate a manual

pushbutton reset switch. The WDI, when enabled, keeps

RESET and RESET from becoming active if it is strobed

table in the configuration register.

Other features include internal chip-enable gating

logic, which accepts a valid CE IN from a microproces-

sor and only gates it through as valid to CE OUT when

the MAX6909/MAX6910 are not in a reset state. This

can be used for disabling CMOS RAM to limit current

consumption when OUT is switched to BATT.

Pin Description

PIN

NAME

FUNCTION

1

BATT

Connect BATT to GND if no backup battery supply is used.

2

OUT

Supply Output for CMOS RAM or Other ICs Requiring Use of Backup Battery Power. Bypass to GND with

at least a 0.1µF capacitor.

3

BATT ON

Logic Output Open Drain. BATT ON is low when the MAX6909/MAX6910 are powered from BATT.

4

CE IN

5

PFI

Power-Fail Comparator Input. For monitoring external power supplies.

6

MR

Manual Reset Input. The active-low input has an internal pullup resistor. Internal debouncing circuitry

ensures noise immunity. Leave open if unused.

7

WDI

Watchdog Input

8

GND

Ground

9X1

32.768kHz Crystal Pin; Oscillator Input

10

X2

32.768kHz Crystal Pin; Oscillator Output

11

CX FAIL

Crystal Fail Output. Open drain, active low.

12

SDA

Serial Data Line. Data input/output connection for the 2-wire serial interface.

13

SCL

Serial Clock Line. Clock input connection for the 2-wire serial interface.

14

ALM

Alarm Output. Open drain, active low.

15

PZT

Piezo Transducer Output. Push-pull Piezo transducer output.

16

PFO

Power-Fail Comparator Output. Push-pull active low.

17

CE OUT

Chip-Enable Output. For controlling external RAM.

18

RESET

Open-Drain, Active-Low Reset Output

19

RESET

Push-Pull, Active-High Reset Output. Complement of RESET.

20

Main Supply Input. Bypass to GND with at least a 0.01µF capacitor.

SuperCap is a trademark of Baknor Industries.