MAX6917EO33 datasheet(7/31 Pages) MAXIM

Part #	MAX6917EO33

Description	I2C-Compatible RTC with Microprocessor Supervisor, Alarm, and NV RAM Controller

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Manufacturer	MAXIM [Maxim Integrated Products]

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I2C-Compatible RTC with Microprocessor

Supervisor, Alarm, and NV RAM Controller

_______________________________________________________________________________________

7

VCC-TO-OUT VOLTAGE vs. TEMPERATURE

TEMPERATURE (

°C)

60

35

10

15

20

25

30

35

40

10

-40

85

VCC = 3V

VBATT = 0V

IOUT = 35mA

VCC = 3.3V

VBATT = 0V

IOUT = 35mA

BATT-TO-OUT VOLTAGE vs. TEMPERATURE

1

2

3

4

5

6

7

8

9

10

0

TEMPERATURE (

°C)

60

35

10

15

-40

85

VCC = 0V

VBATT = 3V

IOUT = 800

µA

VCC = 0V

VBATT = 2V

IOUT = 400

µA

TIMEKEEPING CURRENT

vs. TEMPERATURE

1.0

1.2

1.4

1.6

0.4

0.6

0.8

TEMPERATURE (

°C)

60

35

10

15

-40

85

SCL = SDA = VCC = 0V

1Hz, 32kHz OUTPUTS DISABLED

XTAL FAIL DISABLED

VBATT = 3V

TIMEKEEPING CURRENT

vs. TEMPERATURE

1.0

1.2

1.4

1.6

0.4

0.6

0.8

TEMPERATURE (

°C)

60

35

10

15

-40

85

VBATT = 3V

SCL = SDA = VCC = 0V

1Hz, 32kHz OUTPUTS DISABLED

XTAL FAIL ENABLED

Typical Operating Characteristics

(VCC = 3V, VBATT = 3V, TA = +25°C, unless otherwise noted.)

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

Note 3:

I2C serial interface is operational for VCC > VRST.

Note 4:

See the Detailed Description section (VOUT function).

Note 5:

IBATT is specified with SDA = SCL = VCC, CE_IN = WDI = GND, VOUT , CE_OUT, and MR floating. ICCS is specified with SDA =

SCL = VCC, CE_IN = WDI = GND, VOUT, CE_OUT, and MR floating.

Note 6:

I2C serial interface operating at 400kHz, SDA pulled high, and WDI = VCC or GND, VOUT and CE_OUT floating.

Note 7:

For OUT switchover to BATT, VCC must fall below VRST and VBATT. For OUT switchover to VCC, VCC must be above VRST or

above VBATT.

Note 8:

Guaranteed by design. Not subject to production testing.

Note 9:

All values are referred to VIH (MIN) and VIL(MAX) levels.

Note 10: Minimum SCL clock frequency is limited by the MAX6917 bus timeout feature, which resets the serial bus interface if either

SDA or SCL is held low for 1s to 2s. When using the burst read or write command, all 96 bytes of RAM must be read/written

within the timeout period. See the Timeout Feature section.

Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

Note 12: Cb is the total capacitance of one bus line in pF.

Note 13: The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is

specified at 250ns. This allows series-protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus

lines without exceeding the maximum specified tF.

Note 14: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

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