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DS1374U-33 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # DS1374U-33
Description  I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

DS1374U-33 Datasheet(HTML) 5 Page - Maxim Integrated Products

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I2C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
_____________________________________________________________________
5
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Figure 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Detect to Recognize Inputs
(VCC Rising)
tRPU
(Note 24)
250
ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tF
300
μs
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tR
0
μs
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection.
Note 2:
Limits at -40°C are guaranteed by design and not production tested.
Note 3:
All voltages are referenced to ground.
Note 4:
VBACKUP should not exceed VCC MAX or 3.7V, whichever is greater.
Note 5:
The use of the 250
Ω trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.
Note 6:
Measured at VCC = typ, VBACKUP = 0V, register 09h = A5h.
Note 7:
Measured at VCC = typ, VBACKUP = 0V, register 09h = A6h.
Note 8:
Measured at VCC = typ, VBACKUP = 0V, register 09h = A7h.
Note 9:
SCL only.
Note 10: SDA and SQW and INT.
Note 11: The RST pin has an internal 50k
Ω pullup resistor to VCC.
Note 12: Trickle charger disabled.
Note 13: ICCA—SCL clocking at max frequency = 400kHz.
Note 14: Specified with I2C bus inactive.
Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 16: WDSTR = 1. BBSQW = 1 is required for operation when VCC is below the power-fail trip point (or absent).
Note 17: CB—total capacitance of one bus line in pF.
Note 18: After this period, the first clock pulse is generated.
Note 19: The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIHMIN of the SCL sig-
nal) to bridge the undefined region of the falling edge of SCL.
Note 21: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
≥ to 250ns must be met. This is
automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before
the SCL line is released.
Note 22: Guaranteed by design. Not production tested.
Note 23: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V
≤ VCC ≤ VCC MAX and 1.3V ≤ VBACKUP ≤ 3.7V.
Note 24: This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is
added to this delay.


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