Dual/Triple, Ultra-Low-Voltage, SOT23 µP

Supervisory Circuits

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11

The normal watchdog timeout period (1.12s min)

begins after the first transition on WDI before the con-

clusion of the long initial watchdog period (Figure 2).

During the normal operating mode, the supervisor will

issue a reset pulse for the reset timeout period if the µP

does not update the WDI with a valid transition (high-to-

low or low-to-high) within the standard timeout period

(1.12s min).

Leave WDI unconnected to disable the watchdog timer.

The WDI unconnected-state detector uses a small

(200nA typ) current source. Therefore, do not connect

WDI to anything that will source more than 50nA.

Power-Fail Comparator

PFI is the noninverting input to a comparator. If PFI is

for the power-fail comparator include monitoring prereg-

ulated input of the power supply (such as a battery) or

providing an early power-fail warning so software can

conduct an orderly system shutdown. It can also be

setting the power-fail threshold with a resistor-divider, as

shown in Figure 3. PFI is the input to the power-fail com-

parator. The typical comparator delay is 2µs from PFI to

Ensuring a Valid Reset Output

The MAX6715A–MAX6729A/MAX6797A are guaranteed

pulldown resistor at RST to ground. The resistor value

used is not critical, but it must be large enough not to

old. For most applications, 100k

Ω is adequate. This con-

figuration does not work for the open-drain outputs of the

MAX6715A/MAX6717A/MAX6719A/MAX6721A/

MAX6723A/MAX6725A/MAX6727A/MAX6728A. For push-

pull, active-high RST output connect the external resistor

1.12s MAX

1.12s MAX

35s MAX

WDI

RST

Figure 2. Normal Watchdog Startup Sequence

MAX6728A/

MAX6729A/

MAX6797A

R1

R2

PFI

GND

PFO

R1 + R2

R2

()

MAX6728A/

MAX6729A/

MAX6797A

R1

R2

PFI

GND

PFO

1

R1

1

R2

+-

R1

[]

()

A)

B)

Figure 3. Using Power-Fail Input to Monitor an Additional