µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

_______________________________________________________________________________________

5

TEMPERATURE (

°C)

100

75

50

25

0

-25

25.4

25.8

26.2

26.6

27.0

25.0

-50

125

µs

RESET AND WATCHDOG

TIMEOUT PERIOD vs. SUPPLY VOLTAGE

5.5

5.0

4.0 4.5

2.5 3.0 3.5

2.0

0.44

0.48

0.52

0.56

0.60

0.40

1.5

6.0

Typical Operating Characteristics (continued)

RESET AND WATCHING TIMEOUT

PERIOD vs. SUPPLY VOLTAGE

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

6.5

7.0

7.5

8.0

8.5

9.0

6.0

1.5

6.0

RESET

WATCHDOG

Pin Description

PIN

MAX6746

MAX6747

MAX6748–

MAX6751

MAX6752

MAX6753

NAME

FUNCTION

1—

—

MR

Manual Reset Input. Pull

MR low to manually reset the device. Reset

remains asserted for the reset timeout period after

MR is released.

—

1

—

RESET IN

Reset Input. High-impedance input to the adjustable reset comparator.

Connect RESET IN to the center point of an external resistor-divider to

set the threshold of the externally monitored voltage.

—

—

1

SET0

Logic Input. SET0 selects watchdog window ratio or disables the

watchdog timer. See Table 1.

22

2

SWT

Watchdog Timeout Input.

MAX6746–MAX6751: Connect a capacitor between SWT and ground to

Farads. Extend the basic watchdog timeout period by using the WDS

input. Connect SWT to ground to disable the watchdog timer function.

MAX6752/MAX6753: Connect a capacitor between SWT and ground to

by pinstrapping SET0 and SET1 (Connect SET0 high and SET1 low to

disable the watchdog timer function.) See Table 1.

3

3

3

SRT

Reset Timeout Input. Connect a capacitor from SRT to GND to select

10

4

4

4

GND

Ground