7

FN7606.1

June 4, 2010

I2E Specifications

Offset mismatch-induced spurious

power

No I2E Calibration performed

-70

dBFS

Active Run state enabled

-81

dBFS

I2E Settling Times

I2Epost_t

Calibration settling time for Active

Run state

1000

ms

Minimum Duration of Valid Analog

Input (Note 13)

Allow one I2E iteration of Offset,

Gain and Phase correction

500

µs

Largest Interleave Spur

Run State enabled, in Track Mode

-94

dBc

Run State enabled and previously

settled, in Hold Mode

-82

dBc

Run State enabled, in Track Mode

-89

dBc

Run State enabled and previously

settled, in Hold Mode

-79

dBc

Total Interleave Spurious Power

Active Run State enabled, in Track

-90

dBc

Active Run State enabled, in Track

-85

dBc

Sample Time Mismatch Between Unit

A/Ds

Active Run State enabled, in Track

Mode

30

fs

Gain Mismatch Between Unit A/Ds

0.01

%

Offset Mismatch Between Unit A/Ds

1mV

NOTES:

6. Unless otherwise noted, parameters with Min and/or MAX limits are 100% production tested at their worst case temperature

extreme ( +85°C).

on each digital output.

8. See “Nap/Sleep” for more detail.

9. AC Specifications apply after internal calibration of the A/D is invoked at the given sample rate and temperature. Refer to

“Power-On Calibration” and “User Initiated Reset” for more detail.

10. The DLL Range setting must be changed for low speed operation.

noted.

12. This specification only applies when I2E is in Active Run state, and in Track Mode.

13. Limits are specified over the full operating temperature and voltage range and are established by characterization and not

production tested.

PARAMETER

SYMBOL

CONDITIONS

ISLA110P50

(Note 6)

UNITS

MIN

TYP

MAX

ISLA110P50