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ZM7308G-65507-Q1 Datasheet(PDF) 6 Page - Power-One |
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ZM7308G-65507-Q1 Datasheet(HTML) 6 Page - Power-One |
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6 / 33 page  ZM7300G Series Digital Power Manager Data Sheet ZD-00896 Rev. 5.1, 13-Jul-10 www.power-one.com Page 6 of 33 8.4 I2C Interface Parameter Conditions/Description Min Nom Max Units ViL Input low voltage -0.5 0.3·VDD V ViH Input high voltage 0.7·VDD VDD+0.5 V Vhys Input hysteresis 0.05·VDD V VoL Output low voltage, ISINK=3mA 0 0.4 V tr Rise time for SDA and SCL 20+0.1Cb 1 300 ns tof Output fall time from ViHmin to ViLmax 20+0.1Cb 1 250 ns Ii Input current each I/O pin, 0.1VDD<Vi<0.9VDD -10 10 μA Ci Capacitance for each I/O pin 10 pF fSCL SCL clock frequency 0 400 kHz Standard-Mode I 2C (fSCL ≤ 100kHz) RPU External pull-up resistor 1 1000/Cb 1 kΩ tHDSTA Hold time (repeated) START condition 4.0 μs tLOW Low period of the SCL clock 4.7 μs tHIGH High period of the SCL clock 4.0 μs tSUSTA Setup time for a repeated START condition 4.7 μs tHDDAT Data hold time 0 3.45 μs tSUDAT Data setup time 250 ns tSUSTD Setup time for STOP condition 4.0 μs tSUF Bus free time between a STOP and START condition 4.7 μs Fast-Mode I 2C (100kHz < fSCL≤ 400kHz) RPU External pull-up resistor 1 300/Cb 1 kΩ tHDSTA Hold time (repeated) START condition 0.6 μs tLOW Low period of the SCL clock 1.3 μs tHIGH High period of the SCL clock 0.6 μs tSUSTA Setup time for a repeated START condition 0.6 μs tHDDAT Data hold time 0 0.9 μs tSUDAT Data setup time 100 ns tSUSTD Setup time for STOP condition 0.6 μs tSUF Bus free time between a STOP and START condition 1.3 μs ______________________________________ 1 Cb – bus capacitance in pF, typically from 10pF to 400pF Figure 2. I 2C Timing Parameters tr tLO W tHIG H tLO W tHDST A tSUST A tHDDA T tSUDA T tSUST O tBU F to f SCL SDA |
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