MC54/74HC365

High–Speed CMOS Logic Data

DL129 — Rev 6

3

MOTOROLA

Unit

Guaranteed Limit

VCC

V

Test Conditions

Parameter

Symbol

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Test Conditions

Parameter

Symbol

IOZ

Maximum Three–State

Leakage Current

Output in High–Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0

± 0.5

± 5.0

± 10

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3)

2.0

4.5

6.0

120

24

20

150

30

26

180

36

31

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

2.0

4.5

6.0

220

44

37

275

55

47

330

66

56

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

2.0

4.5

6.0

220

44

37

275

55

47

330

66

56

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

4.5

6.0

60

12

10

75

15

13

90

18

15

ns

Cin

Maximum Input Capacitance

—

10

10

10

pF

Cout

Maximum Three–State Output Capacitance

(Output in High–Impedance State)

—

15

15

15

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Buffer)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Buffer)*

40

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS

VCC

GND

tf

tr

INPUT A

OUTPUT Y

10%

50%

90%

10%

50%

90%

tTLH

tPLH

tPHL

tTHL

OUTPUT ENABLE

OUTPUT Y

OUTPUT Y

50%

50%

50%

90%

10%

tPZL

tPLZ

tPZH tPHZ

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

Figure 1.

Figure 2.