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SSL2103 Datasheet(PDF) 7 Page - NXP Semiconductors |
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SSL2103 Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 21 page SSL2103 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 25 November 2010 7 of 21 NXP Semiconductors SSL2103 SMPS controller IC for dimmable LED lighting The SB_DRV output is activated when the maximum voltage on pin HVDET is below the Vth(SBLEED) level (52 V typically). The WB_DRV output is activated as soon as the voltage on pin ISENSE exceeds the Vth(high)(ISENSE) level (100 mV typically). The WB_DRV output is deactivated when the ISENSE voltage drops below the Vth(low)(ISENSE) level ( 250 mV typically). The WB_DRV output is also deactivated when the strong bleeder switch is switched on. See Figure 5. 8.5 Valley switching A new cycle is started when the primary switch is switched on (see Figure 6). After a time determined by the oscillator voltage, RC and the internal regulation level, the switch is turned off and the secondary stroke starts. The internal regulation level is determined by the voltage on pin PWMLIMIT. After the secondary stroke, the drain voltage shows an oscillation with a frequency of approximately: (2) where: Lp = primary self inductance Cp = parasitic capacitance on drain node As soon as the oscillator voltage is high again and the secondary stroke has ended, the circuit waits for a low drain voltage before starting a new primary stroke. Figure 6 shows the drain voltage together with the valley signal, the signal indicating the secondary stroke and the RC voltage. The primary stroke starts some time before the actual valley at low ringing frequencies, and some time after the actual valley at high ringing frequencies. Fig 5. Bleeder circuit 001aam658 HVDET WB_DRV SB_DRV LOW V DETECT Q R S −0.1 V −0.25 V ISENSE GND INTEGRATED B1 OR 1 2 L p C p ---------------------------------------------- |
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