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ADS1174IPAPR Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1174IPAPR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 39 page SCLK FSYNC DOUT DIN t DOHD t FPW t SCLK t SF t SPW t SPW t FRAME t FPW t FS t DIHD t MSBPD t DIST Bit15(MSB) Bit14 Bit13 t DOPD CLK t CPW t CPW t CS t CLK TIMING REQUIREMENTS: FRAME-SYNC FORMAT ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com TIMING CHARACTERISTICS: FRAME-SYNC FORMAT For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V. SYMBOL PARAMETER MIN TYP MAX UNIT tCLK CLK period (1/fCLK) 37 10,000 ns tCPW CLK positive or negative pulse width 12 ns tCS Falling edge of CLK to falling edge of SCLK –0.25 0.25 tCLK tFRAME Frame period (1/fDATA) (1) 256 2560 tCLK tFPW FSYNC positive or negative pulse width 1 tSCLK tFS Rising edge of FSYNC to rising edge of SCLK 5 ns tSF Rising edge of SCLK to rising edge of FSYNC 5 ns tSCLK SCLK period(2) 1 tCLK tSPW SCLK positive or negative pulse width 0.4 tCLK tDOHD (3) (4) SCLK falling edge to old DOUT invalid (hold time) 10 ns tDOPD (4) SCLK falling edge to new DOUT valid (propagation delay) 31 ns tMSBPD FSYNC rising edge to DOUT MSB valid (propagation delay) 31 ns tDIST New DIN valid to falling edge of SCLK (setup time) 6 ns tDIHD (3) Old DIN valid to falling edge of SCLK (hold time) 6 ns (1) Depends on MODE[1:0] and CLKDIV selection. See Table 4 (fCLK/fDATA). (2) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK. (3) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns. (4) Load on DOUT = 20pF. 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 |
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