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778705-01 Datasheet(PDF) 5 Page - National Instruments Corporation |
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778705-01 Datasheet(HTML) 5 Page - National Instruments Corporation |
5 / 8 page 5 National Instruments • Tel: (800) 813 3693 • info@ni.com • ni.com High-Speed Voltage Output – up to 1 MS/s/Channel, up to 16-Bit, up to 32 Channels These specifications are typical at 25 °C unless otherwise stated. Analog Output Output Characteristics Number of channels NI 6715/6713/6733 ................................... 8 voltage outputs NI 6711/6731............................................. 4 voltage outputs Resolution......................................................... 12 bits, 1 in 4,096 (NI 671x), 16 bits, 1 in 65,536 (NI 673x) FIFO buffer size NI 6713/6733............................................. 16,384 samples NI 6711/6715/6731 ................................... 8,192 samples Data transfers .................................................. DMA, interrupts, programmed I/O DMA modes (PXI/PCI only)............................... Scatter-gather Voltage Output Ranges.............................................................. ±10.0 V, ±AO EXT REF Output coupling ................................................ DC Protection ......................................................... Short-circuit to ground Digital I/O Number of channels......................................... 8 input/output Compatibility .................................................... 5 V TTL/CMOS Power-on state ................................................. Input (high-impedance) Data transfers .................................................. Programmed I/O, DMA (NI 673x), interrupts (NI 673x) Input buffer....................................................... 2048 bytes (NI 673x) Output buffer .................................................... 2048 bytes (NI 673x) Transfer rate ..................................................... 10 Mwords/s (NI 673x) Timing I/O General-Purpose Up/Down Counter/Timers Number of channels......................................... 2 Resolution......................................................... 24 bits Compatibility .................................................... 5 V TTL/CMOS Digital logic levels Base clocks available....................................... 20 MHz and 100 kHz Data transfers .................................................. DMA (except NI 6715), interrupts, programmed I/O DMA modes (PCI/PXI only)............................... Scatter-gather Digital Trigger Purpose Analog output ............................................ Start trigger, gate, clock General-purpose counter/timers ............... Source, gate Source............................................................... PFI <0...9>, RTSI <0...6> (except NI 6715) Slope................................................................. Positive or negative; software selectable Compatibility .................................................... 5 V TTL/CMOS Specifications – NI 671x and NI 673x Level Minimum Maximum Input low voltage 0 V 0.8 V Input high voltage 2 V 5 V Output low voltage (I out = 5 mA) – 0.4 V Output high voltage (I out = -3.5 mA) 4.35 V – Maximum Update Rate (NI 671x/673x) Max Update Rate (NI 6715) Number of Using Local Using Host Using Local Using Host Channels FIFO (kS/s)1 Memory (kS/s)2 FIFO (kS/s)1 Memory (kS/s)2 1 1,000 1,000 1,000 800 2 1,000 1,000 850 400 3 1,000 1,000 750 266 4 1,000 1,000 650 200 5 1,000 1,000 600 160 6 952 1,000 550 133 7 833 869 510 114 8 740 769 480 100 1These numbers apply to continuous waveform generation, and do not change irrespective of the number of devices in the system. 2These numbers may change when using more devices or when other CPU or bus activity is taking place. These specifications are typical at 25 oC unless otherwise stated. Analog Output Output Characteristics Number of channels NI 6722 ...................................................... 8 voltage outputs NI 6723 ...................................................... 32 voltage outputs Resolution......................................................... 13 bits, 1 in 8,192 Max update rate FIFO buffer size................................................. 2,048 samples Data transfers .................................................. DMA, interrupts, programmed I/O DMA modes ..................................................... Scatter gather Voltage Output Ranges.............................................................. ±10 V Output coupling ................................................ DC Protection ......................................................... Short-circuit to ground Digital I/O Number of channels......................................... 8 input/output Compatibility .................................................... TTL/CMOS Power-on state ................................................. Input (high-impedance) Data transfers .................................................. Programmed I/O Timing I/O Number of channels Up/down counter/timers ........................... 2 Frequency scaler........................................ 1 Resolution Up/down counter/timers ........................... 24 bits Frequency scaler........................................ 4 bits Compatibility .................................................... 5 V TTL/CMOS Digital logic levels Data transfers Up/down counter/timers ........................... DMA (scatter-gather), interrupts, programmed I/O Frequency scaler........................................ Programmed I/O Digital Trigger Purpose Analog Output ........................................... Start trigger, gate, clock Counter/timers........................................... Source, gate Source............................................................... PFI <0..9> Compatibility .................................................... 5 V TTL Response .......................................................... Rising or falling edge Specifications – NI 672x Max Update Rate (kS/s) Number of Channels Using Local FIFO1 Using Host PC Memory2 1 800 800 2 714 714 8 476 182 16 333 90.9 24 253 60 32 204 45 1These numbers apply to continuous waveform generation, which allows for the time it takes to reset the FIFO to the beginning when cycling through it. This additional time is not incurred when using host PC memory for waveform generation. The max update rate in FIFO mode does not change regardless of the number of devices in the system. 2These results were measured using an NI 6722/6723 device with a 550 MHz Pentium III machine. These numbers may change when using more devices or when other CPU or bus activity occurs. Level Min Max Input low voltage 0.0 V 0.8 V Input high voltage 2.0 V 5.0 V Output low voltage (Iout = 5 mA) – 0.4 V Output high voltage (Iout = -3.5 mA) 4.35 V – For more detailed specifications, please refer to the product manual. |
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