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SAA7144HL Datasheet(PDF) 1 Page - NXP Semiconductors |
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SAA7144HL Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 64 page  1. General description The SAA7144HL is a combination of four stand alone multistandard video decoders. The SAA7144HL is a pure 3.3 V (5 V tolerant inputs and I/Os) CMOS circuit and a highly integrated circuit for video surveillance applications. All four video decoders are based on the principle of line-locked clock decoding and are able to decode the color of PAL, SECAM and NTSC signals into “CCIR 601” compatible color component values. The SAA7144HL accepts as analog inputs in total eight CVBS sources from TV or VTR (two selectable CVBS sources for each of the four decoders). Each of the four video decoders (A, B, C, D) contains an analog preprocessing circuit including source selection for two CVBS sources, anti-aliasing filter and Analog-to-Digital Converter (ADC), an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder (PAL, NTSC and SECAM), a Brightness Contrast Saturation (BCS) control circuit, a multistandard text slicer see Figure 1 and a 27 MHz VBI data bypass. The integrated high performance multistandard data slicer supports several VBI data standards: • Teletext [WST (World Standard Teletext), CCST (Chinese teletext)] (625 lines) • Teletext [US-WST, NABTS (North American Broadcast Text System) and MOJI (Japanese teletext)] (525 lines) • Closed caption [Europe, US (line 21)] • Wide Screen Signalling (WSS) • Video Programming Signal (VPS) • Time codes (VITC EBU/SMPTE) • HIGH-speed VBI data bypass for Intercast™ application. The circuit is I2C-bus controlled via two I2C-bus interfaces where two video decoders share one I2C-bus interface on different I2C-bus slave addresses. Each of the four video decoders of the SAA7144HL uses a register mapping which is compatible to the SAA7113H register mapping. SAA7144HL Quadruple video input processor Rev. 01 — 21 April 2005 Product data sheet |
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