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M48T129V-85PM1 Datasheet(PDF) 10 Page - STMicroelectronics |
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M48T129V-85PM1 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 28 page Operating modes M48T129V, M48T129Y 10/28 Doc ID 5710 Rev 4 2.2 WRITE mode The M48T129Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. Figure 6. WRITE enable controlled, WRITE AC waveforms Figure 7. Chip enable controlled, WRITE AC waveforms AI02382 tAVAV tWHAX tDVWH DATA INPUT A0-A16 E W DQ0-DQ7 VALID tAVWH tAVEL tWLWH tAVWL tWLQZ tWHDX tWHQX AI02582 tAVAV tEHAX tDVWH A0-A16 E W DQ0-DQ7 VALID tAVEL tAVWL tELEH tWHDX DATA INPUT |
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