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M95040-W Datasheet(PDF) 6 Page - STMicroelectronics |
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M95040-W Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 43 page Description M95040, M95020, M95010 6/43 Doc ID 6512 Rev 8 1 Description The M95040 is a 4 Kbit (512 x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). WRITE instructions are disabled by Write Protect (W). Figure 1. Logic diagram Figure 2. 8-pin package connections 1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1. AI01789C S VCC M95xxx HOLD VSS W Q C D D VSS C HOLD Q SVCC W AI01790D M95xxx 1 2 3 4 8 7 6 5 |
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