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EP1AGX20DF484C6N Datasheet(PDF) 8 Page - Altera Corporation |
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EP1AGX20DF484C6N Datasheet(HTML) 8 Page - Altera Corporation |
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8 / 234 page  2–2 Chapter 2: Arria GX Architecture Transceivers Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Figure 2–1 shows a high-level diagram of the transceiver block architecture divided into four channels. Each transceiver block has: ■ Four transceiver channels with dedicated physical coding sublayer (PCS) and physical media attachment (PMA) circuitry ■ One transmitter PLL that takes in a reference clock and generates high-speed serial clock depending on the functional mode ■ Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from the received serial data stream ■ State machines and other logic to implement special features required to support each protocol Figure 2–2 shows functional blocks that make up a transceiver channel. Figure 2–1. Transceiver Block Channel 1 Channel 0 Channel 2 Supporting Blocks (PLLs, State Machines, Programming) Channel 3 RX1 TX1 RX0 TX0 RX2 TX2 RX3 TX3 REFCLK_1 REFCLK_0 Transceiver Block Arria GX Logic Array Figure 2–2. Arria GX Transceiver Channel Block Diagram Notes to Figure 2–2: (1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA. n = 8 or 10. (2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20. Deserializer Serializer Word Aligner 8B/10B Decoder XAUI Lane Deskew Byte Deserializer 8B/10B Encoder Phase Compensation FIFO Buffer Reference Clock Reference Clock Byte Serializer Phase Compensation FIFO Buffer Rate Matcher PCS Digital Section FPGA Fabric PMA Analog Section Receiver PLL Transmitter PLL Clock Recovery Unit m n n m (1) (2) (2) (1) |
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