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EVAL-ADUC7060QSPZ Datasheet(PDF) 7 Page - Analog Devices |
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EVAL-ADUC7060QSPZ Datasheet(HTML) 7 Page - Analog Devices |
7 / 108 page ADuC7060/ADuC7061 Rev. B | Page 7 of 108 Parameter Test Conditions/Comments Min Typ Max Unit DAC CHANNEL SPECIFICATIONS RL = 5 kΩ, CL = 100 pF Voltage Range 0 VREF V 0 AVDD − 0.2 V DAC 12-BIT MODE DC Specifications13 Resolution 12 Bits Relative Accuracy ±2 LSB Differential Nonlinearity Guaranteed monotonic ±0.2 ±1 LSB Offset Error 1.2 V internal reference ±2 ±15 mV Gain Error VREF range (reference = 1.2 V) ±1 % AVDD range ±1 % Gain Error Mismatch 0.1 % of full scale on DAC DAC 16-BIT MODE1 Only monotonic to 14 bits DC Specifications14 Resolution 14 Bits Relative Accuracy For 14-bit resolution ±3 LSB Differential Nonlinearity Guaranteed monotonic (14 bits) ±0.5 ±1 LSB Offset Error 1.2 V internal reference ±2 ±15 mV Gain Error VREF range (reference = 1.2 V) ±1 % AVDD range ±1 % Gain Error Mismatch 0.1 % of full scale on DAC DAC AC CHARACTERISTICS Voltage Output Settling Time 10 μs Digital-to-Analog Glitch Energy 1 LSB change at major carry (where maximum number of bits simultaneously change in the DAC0DAT register) ±20 nV-sec TEMPERATURE SENSOR1, 15 After user calibration Accuracy MCU in power-down or standby mode ±4 °C Voltage Output at 0°C Typical value 96 mV Voltage Tempco Typical value 0.28 mV/°C Thermal Impedance 48-lead LFCSP 27 °C/W 48-lead LQFP 55 °C/W 32-lead LFCSP 30 °C/W POWER-ON RESET (POR) POR Trip Level1 Refers to voltage at DVDD pin Power-on level 2.0 V Power-down level 2.25 V RESET Timeout from POR Maximum supply ramp between 1.8 V and 2.25 V; after POR trip, DVDD must reach 2.25 V within this time limit 128 ms |
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