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EP1AGX60EF484I6N Datasheet(PDF) 7 Page - Altera Corporation |
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EP1AGX60EF484I6N Datasheet(HTML) 7 Page - Altera Corporation |
7 / 234 page © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 2. Arria GX Architecture Transceivers Arria® GX devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix® II GX device family. Arria GX transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. You can configure the transceiver blocks to support the following serial connectivity protocols (functional modes): ■ PCI Express (PIPE) ■ Gigabit Ethernet (GIGE) ■ XAUI ■ Basic (600 Mbps to 3.125 Gbps) ■ SDI (HD, 3G) ■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps) Transceivers within each block are independent and have their own set of dividers. Therefore, each transceiver can operate at different frequencies. Each block can select from two reference clocks to provide two clock domains that each transceiver can select from. Table 2–1 lists the number of transceiver channels for each member of the Arria GX family. Table 2–1. Arria GX Transceiver Channels Device Number of Transceiver Channels EP1AGX20C 4 EP1AGX35C 4 EP1AGX35D 8 EP1AGX50C 4 EP1AGX50D 8 EP1AGX60C 4 EP1AGX60D 8 EP1AGX60E 12 EP1AGX90E 12 AGX51002-2.0 |
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