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EP1AGX50CF780I6N Datasheet(PDF) 10 Page - Altera Corporation

Part # EP1AGX50CF780I6N
Description  The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers
Download  234 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1AGX50CF780I6N Datasheet(HTML) 10 Page - Altera Corporation

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2–4
Chapter 2: Arria GX Architecture
Transceivers
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Figure 2–3 shows the block diagram of the clock multiplier unit.
The transmitter PLL multiplies the input reference clock to generate the high-speed
serial clock required to support the intended protocol. It implements a half-rate
voltage controlled oscillator (VCO) that generates a clock at half the frequency of the
serial data rate for which it is configured.
Figure 2–4 shows the block diagram of the transmitter PLL.
The reference clock input to the transmitter PLL can be derived from:
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1)
of the associated transceiver block
PLD global clock network (must be driven directly from an input clock pin and
cannot be driven by user logic or enhanced PLL)
Figure 2–3. Clock Multiplier Unit
TX Clock
Gen Block
TX Clock
Gen Block
CMU Block
Reference Clock
from REFCLKs,
Global Clock (1),
Inter-Transceiver
Lines
Transmitter Channels [3:2]
Transmitter
PLL
Transmitter Channels [1:0]
Local Clock
Divider Block
Central Clock
Divider
Block
Local Clock
Divider Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Figure 2–4. Transmitter PLL
Notes to Figure 2–4:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your
selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors).
(2) The global clock line must be driven from an input pin only.
Phase
Frequency
Detector
Charge
Pump + Loop
Filter
up
Voltage
Controlled
Oscillator
/M
(1)
INCLK
/L
(1)
Transmitter PLL
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Inter-Transceiver Lines[2:0]
Global Clock
(2)
High Speed
Serial Clock
To
Inter-Transceiver Lines
down


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