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C8051F912-GU Datasheet(PDF) 7 Page - Silicon Laboratories |
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C8051F912-GU Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 318 page Rev. 1.0 7 C8051F91x-C8051F90x 22.3.SMBus Operation ........................................................................................... 227 22.3.1.Transmitter Vs. Receiver........................................................................ 227 22.3.2.Arbitration............................................................................................... 227 22.3.3.Clock Low Extension.............................................................................. 228 22.3.4.SCL Low Timeout................................................................................... 228 22.3.5.SCL High (SMBus Free) Timeout .......................................................... 228 22.4.Using the SMBus............................................................................................ 229 22.4.1.SMBus Configuration Register............................................................... 230 22.4.2.SMB0CN Control Register ..................................................................... 233 22.4.3.Hardware Slave Address Recognition ................................................... 236 22.4.4.Data Register ......................................................................................... 238 22.5.SMBus Transfer Modes.................................................................................. 239 22.5.1.Write Sequence (Master) ....................................................................... 239 22.5.2.Read Sequence (Master) ....................................................................... 240 22.5.3.Write Sequence (Slave) ......................................................................... 241 22.5.4.Read Sequence (Slave) ......................................................................... 242 22.6.SMBus Status Decoding................................................................................. 242 23. UART0.................................................................................................................... 247 23.1.Enhanced Baud Rate Generation................................................................... 248 23.2.Operational Modes ......................................................................................... 249 23.2.1.8-Bit UART ............................................................................................. 249 23.2.2.9-Bit UART ............................................................................................. 250 23.3.Multiprocessor Communications .................................................................... 250 24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)...................................... 255 24.1.Signal Descriptions......................................................................................... 256 24.1.1.Master Out, Slave In (MOSI).................................................................. 256 24.1.2.Master In, Slave Out (MISO).................................................................. 256 24.1.3.Serial Clock (SCK) ................................................................................. 256 24.1.4.Slave Select (NSS) ................................................................................ 256 24.2.SPI Master Mode Operation ........................................................................... 257 24.3.SPI Slave Mode Operation ............................................................................. 259 24.4.SPI Interrupt Sources ..................................................................................... 259 24.5.Serial Clock Phase and Polarity ..................................................................... 260 24.6.SPI Special Function Registers ...................................................................... 262 25. Timers.................................................................................................................... 270 25.1.Timer 0 and Timer 1 ....................................................................................... 272 25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 272 25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 273 25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 274 25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 275 25.2.Timer 2 .......................................................................................................... 280 25.2.1.16-bit Timer with Auto-Reload................................................................ 280 25.2.2.8-bit Timers with Auto-Reload................................................................ 281 25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 282 25.3.Timer 3 .......................................................................................................... 286 |
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