FS6131

First, the FS6131 is used to sample the output clock with the feedback source clock and set/clear the phase align flag when the two

clocks match to within a feedback source clock period. Then, the clock gobbler is used to delay the output phase relative to the input

phase one VCO clock at a time until a transition on the flag occurs. When a transition occurs, the output and input clocks are phase

aligned.

To enter this mode, set STAT[1] to one and clear STAT[0] to zero. If the CMOS bit is set to one, the LOCK/IPRG pin can display the

flag. The flag is always available under software control by reading back the STAT[1] bit, which will be overwritten by the flag in this

mode.

4.2.4. Feedback Divider Monitoring

The feedback divider clock can be brought out the LOCK/IPRG pin independent of the output clock to allow monitoring of the feedback

divider clock. To enter this mode, set both the STAT[1] and STAT[0] bits to one. The CMOS bit must also be set to one to enable the

LOCK/IPRG pin as an output.

4.3 Loop Gain Analysis

For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and

stability.

The loop gain of a PLL is the product of all of the gains within the loop.

The transfer function of the phase detector and charge pump combination is (in A/rad):

π

2

chgpump

PD

I

K

=

The transfer function of the loop filter is (in V/A):

⎟

⎟

⎟

⎟

⎠

⎞

⎜

⎜

⎜

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

+

+

=

1

2

1

1

1

)

(

sC

R

sC

s

K

LF

LF

The VCO transfer function (in rad/s, and accounting for the phase integration that occurs in the VCO) is:

s

A

s

K

VCO

VCO

1

2

)

(

π

=

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