Electronic Components Datasheet Search |
|
CY7C1311JV18-300BZC Datasheet(PDF) 6 Page - Cypress Semiconductor |
|
CY7C1311JV18-300BZC Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 27 page CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Document Number: 001-12562 Rev. *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description D[x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1311JV18 − D [7:0] CY7C1911JV18 − D [8:0] CY7C1313JV18 − D [17:0] CY7C1315JV18 − D [35:0] WPS Input- Synchronous Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]. NWS0, NWS1 Input- Synchronous Nibble Write Select 0, 1 − Active LOW (CY7C1311JV18 Only). Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device. BWS0, BWS1, BWS2, BWS3 Input- Synchronous Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1911JV18 − BWS 0 controls D[8:0] CY7C1313JV18 − BWS 0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1315JV18 − BWS 0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. A Input- Synchronous Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311JV18, 2M x 9 (4 arrays each of 512K x 9) for CY7C1911JV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313JV18 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1315JV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311JV18 and CY7C1911JV18, 18 address inputs for CY7C1313JV18 and 17 address inputs for CY7C1315JV18. These inputs are ignored when the appropriate port is deselected. Q[x:0] Output- Synchronous Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated. CY7C1311JV18 − Q [7:0] CY7C1911JV18 − Q [8:0] CY7C1313JV18 − Q [17:0] CY7C1315JV18 − Q [35:0] RPS Input- Synchronous Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of four sequential transfers. C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C are used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. C Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C are used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 10 for further details. K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. [+] Feedback |
Similar Part No. - CY7C1311JV18-300BZC |
|
Similar Description - CY7C1311JV18-300BZC |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |