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CY7C1511KV18 Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY7C1511KV18 Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 31 page CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document Number: 001-00435 Rev. *G Page 7 of 31 CQ Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 25. CQ Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 25. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon- nected. DOFF Input PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin is connected to a pull up through a 10 K Ω or less pull up resistor. The device behaves in QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR I timing. TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level. VREF Input- Reference Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. VDD Power Supply Power Supply Inputs to the Core of the Device. VSS Ground Ground for the Device. VDDQ Power Supply Power Supply Inputs for the Outputs of the Device. Pin Definitions (continued) Pin Name I/O Pin Description [+] Feedback |
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