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CY7C1911JV18-250BZI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C1911JV18-250BZI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 27 page  18-Mbit QDR® II SRAM 4-Word Burst Architecture CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-12562 Rev. *D Revised August 04, 2009 Features ■ Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 300 MHz Clock for High Bandwidth ■ 4-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz ■ Two Input Clocks (K and K) for Precise DDR Timing ❐ SRAM uses rising edges only ■ Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches ■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems ■ Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports ■ Separate Port Selects for Depth Expansion ■ Synchronous Internally Self-timed Writes ■ QDR ® II Operates with 1.5 Cycle Read Latency when the Delay Lock Loop (DLL) is enabled ■ Operates like a QDR I device with 1 Cycle Read Latency in DLL Off Mode ■ Available in x8, x9, x18, and x36 configurations ■ Full Data Coherency, providing most current Data ■ Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD ■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ Variable Drive HSTL Output Buffers ■ JTAG 1149.1 Compatible Test Access Port ■ Delay Lock Loop (DLL) for Accurate Data Placement Configurations CY7C1311JV18 – 2M x 8 CY7C1911JV18 – 2M x 9 CY7C1313JV18 – 1M x 18 CY7C1315JV18 – 512K x 36 Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II read and write ports are completely independent of one another. In order to maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1311JV18) or 9-bit words (CY7C1911JV18) or 18-bit words (CY7C1313JV18) or 36-bit words (CY7C1315JV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description 300 MHz 250 MHz Unit Maximum Operating Frequency 300 250 MHz Maximum Operating Current x8 730 665 mA x9 735 675 x18 790 705 x36 895 830 [+] Feedback |
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