Electronic Components Datasheet Search |
|
AT77C102B Datasheet(PDF) 8 Page - ATMEL Corporation |
|
AT77C102B Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 20 page 8 5364C–BIOM–3/07 AT77C102B . Figure 3-1. Reset Table 3-7. Switching Performances The following characteristics are applicable to the operating temperature -40 °C ≤ Ta ≤ +85°C Typical conditions are: nominal voltage; T amb = 25°C; FPCLK = 1 MHz; Duty cycle = 50% C load 120 pF on digital and analog outputs unless otherwise specified Parameter Symbol Test Level Min Typ Max Unit Clock frequency fPCLK I0.5 1 2 MHz Clock pulse width (high) t HCLK I 250 ns Clock pulse width (low) tLCLK I 250 ns Clock setup time (high)/reset falling edge tSetup I0 ns No data change t NOOE IV 100 ns Reset pulse width high tHRST IV 50 ns Table 3-8. 3.3V ±10% Power Supply Parameter Symbol Test Level Min Typ Max Unit Output delay from PCLK to ACKN rising edge t PLHACKN I 145 ns Output delay from PCLK to ACKN falling edge tPHLACKN I 145 ns Output delay from PCLK to data output Dxi tPDATA I 120 ns Output delay from PCLK to analog output AVx t PAVIDEO I 250 ns Output delay from OE to data high-Z tDATAZ IV 34 ns Output delay from OE to data output t ZDATA IV 47 ns tHRST tSETUP Reset RST Clock PCLK |
Similar Part No. - AT77C102B_07 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |