8

5364C–BIOM–3/07

AT77C102B

.

Figure 3-1.

Reset

Table 3-7.

Switching Performances

The following characteristics are applicable to the operating temperature -40

°C ≤ Ta ≤ +85°C

Typical conditions are: nominal voltage; T

C

Parameter

Symbol

Test Level

Min

Typ

Max

Unit

Clock frequency

I0.5

1

2

MHz

Clock pulse width (high)

t

HCLK

I

250

ns

Clock pulse width (low)

I

250

ns

Clock setup time (high)/reset falling edge

I0

ns

No data change

t

NOOE

IV

100

ns

Reset pulse width high

IV

50

ns

Table 3-8.

3.3V ±10% Power Supply

Parameter

Symbol

Test Level

Min

Typ

Max

Unit

Output delay from PCLK to ACKN rising edge

t

PLHACKN

I

145

ns

Output delay from PCLK to ACKN falling edge

I

145

ns

Output delay from PCLK to data output Dxi

I

120

ns

Output delay from PCLK to analog output AVx

t

PAVIDEO

I

250

ns

Output delay from OE to data high-Z

IV

34

ns

Output delay from OE to data output

t

ZDATA

IV

47

ns

tHRST

tSETUP

Reset RST

Clock PCLK