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MAX3825 Datasheet(PDF) 1 Page - Maxim Integrated Products |
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MAX3825 Datasheet(HTML) 1 Page - Maxim Integrated Products |
1 / 8 page General Description The MAX3825 is a quad transimpedance amplifier (TIA) intended for 2.5Gbps system interconnect applications. Each of the four channels converts a small photodiode current to a measurable differential voltage with a tran- simpedance gain of 3.7k Ω. The circuit features 460nARMS of input-referred noise per channel corre- sponding to an optical input sensitivity of -22.3dBm (BER ≤ 1 × 10-14). The quad transimpedance amplifier has 20ps of deterministic jitter and a 2.4GHz small-sig- nal bandwidth. The MAX3825 is optimized for use with a quad PIN photodetector array with a standard fiber pitch of 250µm. The MAX3825 operates from a single +3.3V supply over a 0°C to +85°C temperature range. With a +3.3V supply, each channel dissipates 93mW of power. A DC cancellation circuit on each channel provides a true dif- ferential output swing over a wide range of input cur- rents. Each channel has an independent supply and ground to allow all or any combination of channels to be con- nected. This device is available in dice only. Features o Single +3.3V Supply o 93mW per Channel Power Dissipation o 460nARMS Input-Referred Noise o 20ps Deterministic Jitter o 2.4GHz Small-Signal Bandwidth o No External Compensation o 40dB Power-Supply Rejection Ratio o Compact Die with 250µm Channel Pitch o 100Ω Differential Output Impedance Applications +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects ________________________________________________________________ Maxim Integrated Products 1 19-1855 Rev 0; 11/00 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Ordering Information Dice* PIN-PACKAGE TEMP. RANGE 0°C to +85°C MAX3825U/D PART Typical Operating Circuit appears at end of data sheet. *Dice are designed to operate with a 0°C to +120°C junction temperature, but are tested and guaranteed only at TA = +25°C. Chip Topography/Pad Configuration VCCO1 OUT1+ OUT1- VCCO1 VCCO2 OUT2+ OUT2- VCCO2 VCCO3 OUT3+ OUT3- VCCO3 VCCO4 OUT4+ OUT4-VCCO4 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GNDO3 GNDO4 VCCI4 VCCI3 GNDI3 GNDI4 ENABLE 19 18 20 15 14 16 17 N.C. N.C. FILTER IN1 FILT1 IN2 FILT2 IN3 FILT3 IN4 FILT4 N.C. N.C. 12 3 4 5 6 7 8 9 10 11 12 13 GNDO1 GNDO2 GNDF GNDI2 VCCI2 VCCI1 GNDI1 VCCFILT 37 38 39 40 41 42 43 44 N.C. System Interconnects SDH/SONET Backplanes Dense Digital Cross- Connects ATM Switching Networks High-Speed Parallel Optical Links |
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