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MAX3891 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX3891 Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 12 page Pin Description PIN NAME FUNCTION 1, 17, 33, 48, 49, 63 GND Ground 2, 5, 7, 10, 13, 14, 19, 21, 23, 25, 27, 29, 31, 32, 35, 37, 39, 41, 43, 45, 47, 51, 53, 56, 60, 64 VCC +3.3V Supply Voltage 3 SLBO- System Loopback Negative Output. Enabled when SOS is high. 4 SLBO+ System Loopback Positive Output. Enabled when SOS is high. 6 SOS System Loopback Output Select, TTL Input. System loopback disabled when low. 8 SCLKO- Negative PECL Serial Clock Output 9 SCLKO+ Positive PECL Serial Clock Output 11 SDO- Negative PECL Serial Data Output 12 SDO+ Positive PECL Serial Data Output 15 PCLKI+ Positive PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 16 PCLKI- Negative PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 18, 20, 22, 24, 26, 28, 30, 34, 36, 38, 40, 42, 44, 46, 50, 52 PDI15 to PDI0 Single-Ended PECL Parallel Data Inputs. Data is clocked on the PCLKI positive transition. PDI15 is transmitted first. 54 PCLKO+ Positive PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. 55 PCLKO- Negative PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. 57 RCLK+ Positive Reference Clock Input. Connect a PECL-compatible crystal reference clock to the RCLK inputs. 58 RCLK- Negative Reference Clock Input. Connect a PECL-compatible crystal reference clock to the RCLK inputs. 59 CLKSET Reference Clock Rate Programming Pin: CLKSET = VCC: Reference Clock Rate = 155.52MHz CLKSET = Open: Reference Clock Rate = 77.76MHz CLKSET = 20k Ω to GND: Reference Clock Rate = 51.84MHz CLKSET = GND: Reference Clock Rate = 38.88MHz 61 FIL- Filter Capacitor Input. Connect a 0.33 µF capacitor between FIL+ and FIL- 62 FIL+ Filter Capacitor Input. Connect a 0.33 µF capacitor between FIL+ and FIL- EP Exposed Pad Ground. This must be soldered to a circuit board for proper electrical and thermal performance (see exposed pad package information). 16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs 4 _______________________________________________________________________________________ |
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