MAX3891ECB datasheet(6/12 Pages) MAXIM

Part #	MAX3891ECB

Description	16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET with Clock Synthesis and LVPECL Inputs

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Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

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6 / 12 page

16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET,

with Clock Synthesis and LVPECL Inputs

6

_______________________________________________________________________________________

Applications Information

Setup and Hold Time Requirements

The setup and hold-time specifications assume that the

parallel clock-input signal (PCLKI) and parallel-data

input signal (PDI_) are from the same source. They

should have identical common-mode voltages, signal

amplitudes, and slew rates. If PCLKI and PDI_ differ

significantly, the setup and hold-time requirements

must be modified to account for these differences.

Define tDEG as the adjustment to the setup and hold-

time requirement when there are significant differences

between PCLKI and PDI_.

where tT is the transition time (20%–80%) of the paral-

lel-data and clock-input signals, VOH and VOL are the

input high and low voltage, respectively, of the parallel-

data and clock-input signals, and VCMDIFF is the differ-

ence in common-mode voltages of the parallel-data

and clock-input signals.

t

VCM

t

VV

DEG

DIFF

T

OH

OL

=×









06

.

-

MAX3891

16-BIT

PARALLEL

INPUT

REGISTER

16-BIT

PARALLEL

SHIFT

REGISTER

PHASE/FREQ

DETECT

PECL

PDI15

PDI1

PDI0

PCLKI+

PCLKI-

RCLK+

RCLK-

PECL

BUF

PECL

CML

SLBO+

SOS

SDO+

SDO-

SLBO-

SCLKO+

SCLKO-

PECL

SHIFT

LATCH

FILTER

FIL+ FIL- CLKSET

PCLKO+ PCLKO-

PRESCALER

VCO

DIVIDE

BY 16

Figure 2. Functional Block Diagram

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