IEEE 802.3af PD Interface Controller

For Power-Over-Ethernet

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3

Note 1:

All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design.

Note 2:

The input offset current is illustrated in Figure 1.

Note 3:

resistance. See Figure 1.

Note 4:

Classification current is turned off whenever the IC is in power mode.

Note 5:

Note 6:

See the Thermal Dissipation section for details.

Note 7:

When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k

Ω (±1%), the turn-

on threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO

Note 8:

Note 9:

MAX5940A/MAX5940B/MAX5940C/MAX5940D to exit power-on mode (as long as the input voltage remains above an opera-

ble voltage level of 12V).

Note 10: Guaranteed by design.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

UVLO Input Ground Sense

Threshold (Note 8)

50

440

mV

UVLO Input Ground Sense Glitch

Rejection

7µs

Power Turn-Off Voltage,

Undervoltage Lockout Deglitch

Time (Note 9)

0.32

ms

(Note 10)

0.6

1.1

Isolation Switch N-Channel

MOSFET On-Resistance

Output current =

measured between

0.8

1.5

Ω

Isolation Switch N-Channel

MOSFET Off-Threshold Voltage

< 1µA

0.5

V

GATE Pulldown Switch Resistance

38

80

Ω

GATE Charging Current

5

10

15

µA

GATE High Voltage

5.59

5.76

5.93

V

1.16

1.23

1.31

V

Threshold

Hysteresis

70

mV

4.62

4.76

4.91

V

Threshold

Hysteresis

80

mV

PGOOD, PGOOD Output Low

Voltage (Note 11)

≤

(GND - 5V)

0.4

V

PGOOD Leakage Current (Note 11)

1

µA

PGOOD Leakage Current (Note 11)

1

µA

ELECTRICAL CHARACTERISTICS (continued)

°C to +85°C, unless otherwise noted.