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MAX5442AEUB Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX5442AEUB Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 12 page +3V/+5V, Serial-Input, Voltage-Output, 16-Bit DACs 8 _______________________________________________________________________________________ to a standard R-2R ladder, allowing unbuffered opera- tion in medium-load applications. The MAX5442/MAX5444 provide matched bipolar offset resistors, which connect to an external op amp for bipo- lar output swings (Figure 2b). Digital Interface The MAX5441–MAX5444 digital interface is a standard 3-wire connection compatible with SPI/QSPI/ MICROWIRE interfaces. The chip-select input (CS) frames the serial data loading at the data-input pin (DIN). Immediately following CS’s high-to-low transition, the data is shifted synchronously and latched into the input register on the rising edge of the serial clock input (SCLK). After 16 data bits have been loaded into the serial input register, it transfers its contents to the DAC latch on CS’s low-to-high transition (Figure 3). Note that if CS is not kept low during the entire 16 SCLK cycles, data will be corrupted. In this case, reload the DAC latch with a new 16-bit word. Clearing the DAC A 20ns (min) logic-low pulse on CLR asynchronously clears the DAC buffer to code 0 in the MAX5441/ MAX5443 and to code 32768 in the MAX5442/ MAX5444. External Reference The MAX5441–MAX5444 operate with external voltage references from 2V to VDD. The reference voltage determines the DAC’s full-scale output voltage. Power-On Reset The power-on reset circuit sets the output of the MAX5441/MAX5443 to code 0 and the output of the MAX5442/MAX5444 to code 32768 when VDD is first applied. This ensures that unwanted DAC output volt- ages will not occur immediately following a system power-up, such as after a loss of power. Applications Information Reference and Ground Inputs The MAX5441–MAX5444 operate with external voltage references from 2V to VDD, and maintain 16-bit perfor- mance if certain guidelines are followed when selecting and applying the reference. Ideally, the reference’s temperature coefficient should be less than 0.1ppm/°C to maintain 16-bit accuracy to within 1LSB over the -40°C to +85°C extended temperature range. Since this converter is designed as an inverted R-2R volt- age-mode DAC, the input resistance seen by the voltage reference is code-dependent. In unipolar mode, the worst-case input-resistance variation is from 11.5kΩ (at code 8555hex) to 200kΩ (at code 0000hex). The maxi- mum change in load current for a 2.5V reference is 2.5V / 11.5k Ω = 217µA; therefore, the required load regulation is 7ppm/mA for a maximum error of 0.1LSB. This implies a reference output impedance of less than 18mΩ. In addition, the impedance of the signal path from the volt- age reference to the reference input must be kept low because it contributes directly to the load-regulation error. The requirement for a low-impedance voltage reference is met with capacitor bypassing at the reference inputs and ground. A 0.1µF ceramic capacitor with short leads between REF and GND provides high-frequency bypassing. A surface-mount ceramic chip capacitor is preferred because it has the lowest inductance. An ; ; ;; CS SCLK DIN MSB LSB D15 D8 D7 D6 D5 D4 D3 D2 D1 D0 SUB-BITS DAC UPDATED D14 D13 D12 D11 D10 D9 Figure 3. MAX5441–MAX5444 3-Wire Interface Timing Diagram |
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