MAX9210EUM datasheet(4/17 Pages) MAXIM

Part #	MAX9210EUM

Description	Programmable DC-Balance 21-Bit Deserializers

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Manufacturer	MAXIM [Maxim Integrated Products]

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Programmable DC-Balance

21-Bit Deserializers

4

_______________________________________________________________________________________

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except VTH and VTL.

Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production

tested at TA = +25°C.

Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.

Note 4: CL includes probe and test jig capacitance.

Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP.

Note 6: RSKM measured with

≤150ps cycle-to-cycle jitter on RxCLK IN.

AC ELECTRICAL CHARACTERISTICS

(VCC = VCCO = +3.0V to +3.6V, 100mVP-P at 200kHz supply noise, CL = 8pF, PWRDWN = high, DCB/NC = high or low, differential

input voltage |VID| = 0.1V to 1.2V, Input Common Mode Voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise

noted. Typical values are at VCC = VCCO = +3.3V, |VID| = 0.2V, VCM = 1.25V, TA = 25°C). (Notes 3, 4, 5)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

RxOUT_

3.52

5.04

6.24

MAX9210/

MAX9220

RxCLK OUT

2.2

3.15

3.9

Output Rise Time

CLHT

0.1VCCO

to

0.9VCCO,

Figure 3

MAX9214/MAX9222

2.2

3.15

3.9

ns

RxOUT_

1.95

3.18

4.35

MAX9210/

MAX9220

RxCLK OUT

1.3

2.12

2.9

Output Fall Time

CHLT

0.9VCCO

to

0.1VCCO,

Figure 3

MAX9214/MAX9222

1.3

2.12

2.9

ns

8MHz

6600

7044

16MHz

2560

3137

34MHz

900

1327

DC-balanced mode,

Figure 4 (Note 6)

66MHz

330

685

10MHz

6600

7044

20MHz

2500

3300

40MHz

960

1448

RxIN Skew Margin

RSKM

Non-DC-balanced mode,

Figure 4 (Note 6)

85MHz

330

685

ps

RxCLK OUT High Time

RCOH

Figures 5a, 5b

0.35 x

RCOP

ns

RxCLK OUT Low Time

RCOL

Figures 5a, 5b

0.35 x

RCOP

ns

RxOUT Setup to RxCLK OUT

RSRC

Figures 5a, 5b

0.30 x

RCOP

ns

RxOUT Hold from RxCLK OUT

RHRC

Figures 5a, 5b

0.45 x

RCOP

ns

RxCLK IN to RxCLK OUT Delay

RCCD

Figures 6a, 6b

4.9

6.17

8.1

ns

Deserializer Phase-Locked Loop

Set

RPLLS

Figure 7

32800

x RCIP

ns

Deserializer Power-Down Delay

RPDD

Figure 8

100

ns

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