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TDA5150 Datasheet(PDF) 18 Page - Infineon Technologies AG |
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TDA5150 Datasheet(HTML) 18 Page - Infineon Technologies AG |
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18 / 106 page  TDA 5150 TDA 5150 Functional Description Data Sheet 18 V 1.0, July 2009 • The data encoder synchronizes the bitstream to be transmitted with the internal bit clock. It supports different types of Manchester and Bi-Phase encodings and is able to generate PRBS9 pseudo-random patterns. The internal data encoder can be bypassed, allowing transmissions in direct (transparent) mode. • The core element of the transmitter is the sigma-delta fractional-N PLL Synthesizer, used for carrier frequency control and as part of the digital modulator as well. It covers the frequency bands 300-320 MHz, 425-450 MHz and 863-928 MHz with outstanding frequency resolution. Only one, fixed frequency crystal (e.g. 13 MHz) is required for reference frequency generation. The synthesizer is characterized by short settling time. It is also used as direct FSK modulator, and together with a Gaussian filter, implemented by means of lookup table offers the functionality of a direct GFSK modulator. • The integrated Power Amplifier is able to deliver up to +10dBm output power into a 50 Ω load (usually the antenna) via an external impedance matching network. In addition there are integrated capacitors, connected between GND and the RF-PA output, over SFR controlled on/off switches. These capacitors are elements of a software controlled antenna tuner. They may be used to fine-tune (adjust) the PA- output to Load matching network impedance, and thus to maintain good VSWR values over a wider frequency band. This is particularly useful if the transmitter is operated not only on a single frequency but in a given frequency band. 2.4 Functional Description 2.4.1 Special Function Registers TDA 5150 is configurable by programming the Special Function Register bank (abbreviated SFRs) via the SPI interface. Terminology and notations related to TDA5150 SFR set, list of symbols and programming restrictions are given in Chapter 22 Register Terminology. Detailed description of SFR map, programming, usage and content explanations are found in the following chapters (§2.4.x.x and §2.5.x.x). See also Chapter 2.5.1 SFR Register List . 2.4.2 Power Supply Circuit An internal voltage regulator generates a constant supply voltage (2.1V nominal) for most of the analog and digital blocks. An external capacitor (100nF nominal value) connected between VREG (pin 4) and GND (pin 3) is necessary to guarantee stable functionality of the regulator. The regulated voltage on VREG pin is not adjustable by user and it is not allowed to connect any additional, external loads to this pin, but the above mentioned decoupling capacitor. |
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