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IR3508ZMPBF Datasheet(PDF) 7 Page - International Rectifier |
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IR3508ZMPBF Datasheet(HTML) 7 Page - International Rectifier |
7 / 19 page IR3508Z Page 7 of 19 Jan 09, 2009 SYSTEM THEORY OF OPERATION System Description The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three analog buses, i.e., DAC, EA, and IOUT. The digital buses are responsible for switching frequency determination and accurate phase timing control without any external components. The analog buses are used for PWM control and current sharing between interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK signals, error amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by the converter of each phase, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, phase disable circuit, current sensing and sharing, etc. PWM Control Method The PWM block diagram of the XPhase3 TM architecture is shown in Figure 1. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain and wide-bandwidth voltage type error amplifier is implemented in the controller’s design to achieve a fast voltage control loop. Input voltage is sensed by the phase ICs to provide feed- forward control. The feed-forward control compensates the ramp slope based on the change in input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. PWM COMPARATOR RDRP1 OFF VSETPT CLKIN RCS CCS ISHARE PHSIN DACIN VCC CSIN+ GATEL EAIN GATEH CBST VCCH CSIN- SW PGND VCCL RTHRM VID6 PHSOUT VID6 RCOMP OFF CLK D Q PHSIN PSI CCOMP OFF VID6 RFB VID6 + - CLKIN CDRP RCS CCS RDRP 3K GND VOUT DACIN VCC VDAC VO LGND IOUT PHSIN VOSNS- VOSNS+ GATEL EAIN GATEH IIN VDRP VIN FB EAOUT CLKOUT CSIN- CSIN+ IROSC VID6 VDAC REMOTE SENSE AMPLIFIER VCCH CBST CLK D Q Q DFFRH VCCL GATE DRIVE VOLTAGE PHSOUT PWM COMPARATOR VID6 VID6 PSI VID6 CLK D Q + - 3K VID6 CLK D Q Q U248 DFFRH VID6 + VID6 + - + BODY BRAKING COMPARATOR RAMP DISCHARGE CLAMP ENABLE CURRENT SENSE AMPLIFIER RVSETPT PWM LATCH SHARE ADJUST ERROR AMPLIFIER RESET DOMINANT 1 2 PHASE IC PGND VID6 PSI - + SW VID6 + + Thermal Compensation ENABLE RAMP DISCHARGE CLAMP VDRP AMP VDAC BODY BRAKING COMPARATOR VN IVSETPT CLOCK GENERATOR PWM LATCH CURRENT SENSE AMPLIFIER IMON ERROR AMPLIFIER SHARE ADJUST ERROR AMPLIFIER RESET DOMINANT RFB1 COUT CONTROL IC CFB 1 2 PSI PHASE IC PHSOUT OFF VID6 Figure 1: PWM Block Diagram |
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