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IR3523MPBF Datasheet(PDF) 3 Page - International Rectifier |
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IR3523MPBF Datasheet(HTML) 3 Page - International Rectifier |
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3 / 37 page  IR3523 Page 3 of 37 June 20, 2008 PIN# PIN SYMBOL PIN DESCRIPTION 12 FB2 Output 2 Error Amplifier inverting input 13 VOUT2 Output 2 remote sense amplifier output. 14 VOSEN2+ Output 2 remote sense amplifier input. Connect to output at the load. 15 VOSEN2- Output 2 remote sense amplifier input. Connect to ground at the load. 16 VOSEN1- Output 1 remote sense amplifier input. Connect to ground at the load. 17 VOSEN1+ Output 1 remote sense amplifier input. Connect to output at the load. 18 VOUT1 Output 1 remote sense amplifier output. 19 FB1 Inverting input to the output 1 Error Amplifier 21 EAOUT1 Output 1 error amplifier output 22 OCSET1 Programs the output 1 constant converter output current limit and hiccup over- current threshold through an external resistor tied to VDAC1 and an internal current source from this pin. Over-current protection can be disabled by connecting a resistor from this pin to VDAC1 to program the threshold higher than the possible signal into the IIN pin from the phase ICs but no greater than 5V (do not float this pin as improper operation will occur). 23 VDAC1 Output 1 reference voltage programmed by the VID inputs and error amplifier non-inverting input. Connect an external RC network to LGND to program dynamic VID slew rate and provide compensation for the internal buffer amplifier. 24 SS/DEL1 Programs output 1 startup and over current protection delay timing. Connect an external capacitor to LGND to program. 25 IIN1 Output 1 average current input from the output 1 phase IC(s). This pin is also used to communicate over voltage condition to phase ICs. 26 VDRP1 Output 1 Buffered IIN signal. Connect an external RC network to FB1 to program converter output impedance. 27 ROSC/OVP Connect a resistor to LGND to program oscillator frequency and OCSET, VDAC1 and VREF2 bias currents. Oscillator frequency equals switching frequency per phase. The pin voltage is 0.6V during normal operation and higher than 1.6V if over-voltage condition is detected. 28 PG1 Open collector output. Asserted when Output 1 is regulated. 29 LGND Local Ground for internal circuitry and IC substrate connection. 31 CLKOUT Clock output at switching frequency multiplied by phase number. Connect to CLKIN pins of phase ICs. 32 PHSOUT Phase clock output at switching frequency per phase. Connect to PHSIN pin of the first phase IC. 33 PHSIN Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC. 34 VCCL Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a decoupling capacitor to LGND. 35 VCCLFB Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator is programmed by the resistor divider connected to VCCL. 36 VCCLDRV Output of the VCCL regulator error amplifier to control external transistor. The pin senses the converter input voltage through a resistor. 37 PG2 Open collector output. Asserted when Output 2 output is regulated. 38, 39, 40 VID2_0, VID2_1, VID2_2 VID inputs for Output 2 |
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