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SPA21N50C3 Datasheet(PDF) 3 Page - Infineon Technologies AG |
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SPA21N50C3 Datasheet(HTML) 3 Page - Infineon Technologies AG |
3 / 14 page 200 9-12-22 Rev. 3.2 page 3 SPP21N50C 3 SPI21N50C3, SPA21N50C3 Electrical Characteristics Parameter Symbol Conditions Values Unit min. typ. max. Transconductance gfs VDS≥2*ID*RDS(on)max, ID=13.1A - 18 - S Input capacitance Ciss VGS=0V, VDS=25V, f =1MHz - 2400 - pF Output capacitance Coss - 1200 - Reverse transfer capacitance Crss - 30 - Effective output capacitance,5) energy related Co(er) VGS=0V, VDS=400V - 87 - Effective output capacitance,6) time related Co(tr) - 181 - Turn-on delay time td(on) VDD=380V, VGS=0/10V, ID=21A, RG=3.6Ω - 10 - ns Rise time tr - 5 - Turn-off delay time td(off) - 67 - Fall time tf - 4.5 - Gate Charge Characteristics Gate to source charge Qgs VDD=380V, ID=21A - 10 - nC Gate to drain charge Qgd - 50 - Gate charge total Qg VDD=380V, ID=21A, VGS=0 to 10V - 95 - Gate plateau voltage V(plateau) VDD=380V, ID=21A - 5 - V 1Limited only by maximum temperature 2Repetitve avalanche causes additional power losses that can be calculated as P AV=EAR*f. 3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. 4Soldering temperature for TO-263: 220°C, reflow 5C o(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 6C o(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 7I SD<=ID, di/dt<=200A/us, VDClink=400V, Vpeak<VBR, DSS, Tj<Tj,max. Identical low-side and high-side switch. |
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