External Reference

An external reference is required for both the MAX144

and the MAX145. At REF, the DC input resistance is a

minimum of 18k

Ω. During a conversion, a reference

must be able to deliver 250µA of DC load current and

have an output impedance of 10

Ω or less. Use a 0.1µF

bypass capacitor for best performance. The reference

50mV, although noise levels will decrease effective res-

olution at lower reference voltages.

Automatic Power-Down Mode

Whenever the MAX144/MAX145 are not selected

mode. In shutdown all internal circuitry turns off, reduc-

ing supply current to typically less than 0.2µA. With an

external reference stable to within 1LSB, the wake-up

time is 2.5µs. If the external reference is not stable with-

in 1LSB, the wake-up time must be increased to allow

the reference to stabilize.

__________Applications Information

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital

samples, the theoretical maximum SNR is the ratio of

full-scale analog input (RMS value) to the RMS quanti-

zation error (residual error). The ideal, theoretical mini-

mum analog-to-digital noise is caused by quantization

error only and results directly from the ADC’s resolution

(N bits):

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reference noise, clock jitter,

etc. Therefore, SNR is computed by taking the ratio of

the RMS signal to the RMS noise which includes all

spectral components minus the fundamental, the first

five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is the ratio of the fundamental input frequency’s

RMS amplitude to RMS equivalent of all other ADC out-

put signals:

Effective Number of Bits (ENOB)

ENOB indicates the global accuracy of an ADC at a

specific input frequency and sampling rate. An ideal

ADC’s error consists only of quantization noise. With an

input range equal to the full-scale range of the ADC, the

effective number of bits can be calculated as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first five harmon-

ics of the input signal to the fundamental itself. This is

expressed as:

harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the fundamental

(maximum signal component) to the RMS value of the

next largest spurious component, excluding DC offset.

Connection to Standard Interfaces

The MAX144/MAX145 interface is fully compatible with

SPI, QSPI, and MICROWIRE standard serial interfaces.

If a serial interface is available, establish the CPU’s seri-

al interface as master so that the CPU generates the

serial clock for the MAX144/MAX145. Select a clock fre-

quency from 100kHz to 2.17MHz (external clock mode).

1) Use a general-purpose I/O line on the CPU to pull

CS/SHDN low while SCLK is low.

fied before activating SCLK.

3) Activate SCLK for a minimum of 16 clock cycles.

The serial data stream of three leading ones, the

channel identification, and the MSB of the digitized

input signal begin at the first falling clock edge.

DOUT transitions on SCLK’s falling edge and is

available in MSB-first format. Observe the SCLK to

THD = 20 x log

V+ V+ V

+ V

V

22

32

42

52

1

































SINAD(dB) = 20 x log

(Noise + Distortion)

RMS













+2.7V, Low-Power, 2-Channel, 108ksps,

Serial 12-Bit ADCs in 8-Pin µMAX

10

______________________________________________________________________________________

Table 1. Serial Output Data Stream for Internal and External Clock Mode

SCLK CYCLE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DOUT (Internal Clock)

EOC

1

1

CHID D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DOUT (External Clock)

1

1

1

CHID D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0