+2.7V, Low-Power, 2-Channel, 108ksps,

Serial 12-Bit ADCs in 8-Pin µMAX

4

_______________________________________________________________________________________

TIMING CHARACTERISTICS (Figure 7)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Wake-Up Time

2.5

µs

CS/SHDN Fall to Output Enable

tDV

CL = 100pF

120

ns

CS /SHDN Rise to Output Disable

tTR

CL = 100pF, Figure 1

120

ns

SCLK Fall to Output Data Valid

tDO

CL = 100pF, Figure 1

20

120

ns

External clock

0.1

2.17

SCLK Clock Frequency

fSCLK

Internal clock, SCLK for data transfer only

0

5

MHz

External clock

215

SCLK Pulse Width High

tCH

Internal clock, SCLK for data transfer only

(Note 8)

50

ns

External clock

215

SCLK Pulse Width Low

tCL

Internal clock, SCLK for data transfer only

(Note 8)

50

ns

SCLK to

CS /SHDN Setup

tSCLKS

60

ns

CS /SHDN Pulse Width

tCS

60

ns

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been

calibrated.

Note 3: Offset nulled.

Note 4: "On" channel is grounded; sine wave applied to "off" channel (MAX144 only).

Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.

Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 8: Guaranteed by design. Not subject to production testing.