MC9328MX21CVM datasheet(8/100 Pages) FREESCALE

Part #	MC9328MX21CVM

Description	266 MHz i.MX family of microprocessors

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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MC9328MX21 Technical Data, Rev. 3.4

8

Freescale Semiconductor

Signal Descriptions

CSI_VSYNC

Sensor port vertical sync

CSI_HSYNC

Sensor port horizontal sync

CSI_PIXCLK

Sensor port data latch clock

LCD Controller

LD [17:0]

LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals are

multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is multiplexed with

BMI_WRITE of BMI. LD[16] is multiplexed with BMI_READ_REQ of BMI and EXT_DMAGRANT.

FLM_VSYNC

(or simply referred

to as VSYNC)

Frame Sync or Vsync—This signal also serves as the clock signal output for gate

driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with BMI_RXF_FULL

and BMI_WAIT of the BMI.

LP_HSYNC (or simply

referred to as HSYNC)

Line Pulse or HSync

LSCLK

Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI.

OE_ACD

Alternate Crystal Direction/Output Enable.

CONTRAST

This signal is used to control the LCD bias voltage as contrast control. This signal is multiplexed with the

BMI_READ from BMI.

SPL_SPR

Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.

PS

Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the

SLCDC1_CS.

CLS

Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This

signal is multiplexed with the SLCDC1_RS.

REV

Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is

multiplexed with SLCDC1_D0.

Smart LCD Controller

SLCDC1_CLK

SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These are

SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.

SLCDC1_CS

SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal locations.

These are PS and SD2_CMD signals of LCDC and SD2, respectively.

SLCDC1_RS

SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal

locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.

SLCDC1_D0

SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations.

These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is inactive when a

parallel data interface is used.

SLCDC1_DAT[15:0] SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are

multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further

alternate muxing of these signals are available on some of the USB OTG and USBH1 signals.

SLCDC2_CLK

SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with SSI3_CLK

signal from SSI3.

SLCDC2_CS

SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with

SSI3_TXD signal from SSI3.

SLCDC2_RS

SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with

SSI3_RXD signal from SSI3.

Table 2. i.MX21 Signal Descriptions (Continued)

Signal Name

Function/Notes

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