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MC143416PB Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MC143416PB Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 24 page  MC143416 MOTOROLA 8 AG0+, AG1+, AG0–, and AG1– Outputs of Input Amplifier for Codec 0 and Codec 1 (Pins 40, 29, 37, and 32, Respectively) These pins are the differential outputs of the input gain set- ting amplifiers. AO0+, AO1+, AO0–, and AO1– Analog Outputs for Codec 0 and Codec 1 (Pins 44 ,25, 43, and 26, Respectively) These pins are the non–inverting and inverting outputs of the analog output amplifier. This unity gain line driver repre- sents the final stage of the D/A section of the codec. This am- plifier provides a differential output that can be dc–coupled with a hybrid circuit and is able to drive a telephone line. SSI PORT 0 and PORT 1 SCLK0 and SCLK1 Serial Port 0 and Serial Port 1 Clock Signal Output Pins (Pins 11 and 17, Respectively) These pins are the timing reference for the transmission of data through the STx and SRx pins. Data transfer can only happen if the synchronization frame begins. SSYNC0 and SSYNC1 Serial Port 0 and Serial Port 1 Sync Signal Output Pins (Pins 10 and 16, Respectively) These pins output the synchronization frame. The sync signal defines the beginning of each word transmitted through the STx and SRx pins. STx0 and STx1 Serial Port 0 and Serial Port 1 Output Pins (Pins 12 and 18, Respectively) These pins are used to transmit data from serial ports 0 and 1. Serial transmission data is shifted on the rising edge of the serial clock (SCLK). SRx0 and SRx1 Serial Port 0 and Serial Port 1 Input Pins (Pins 13 and 19, Respectively) These pins are used to receive data from serial ports 0 and 1. Serial receive data is sampled internally on the falling edge of the serial clock. RESET RESET System Reset Input (Pin 8) This pin is used to force a hardware reset of the MC143416. Note: This is ineffective when the device is in general power down. RSTEXT External Reset Output to Board Functions from Power Monitor (Pin 9) The MC143416 provides a voltage level sensing circuit which generates an active low external reset when the power supply voltage drops below a nominal 4.5 V. The power on reset (POR) does not reset the internal circuitry, but provides an external reset signal for board use. The minimum duration of the external reset is 140 ms. CLOCKING XTALin, XTALout Crystal Oscillator Input and Output (Pins 2 and 3, Respectively) These pins form a reference oscillator when connected to terminals of an external parallel–resonant crystal. The inter- nal logic clock timing (system clock) is always derived from the XTALin clock signal. The timing for the codecs can be derived from either the XTALin signal, or from the MCLK in- put. Frequency–setting capacitors of appropriate values, as recommended by the crystal supplier, are connected from each pin to ground. The MC143416 has an inverter between XTALin and XTALout. An external resistor below 5 M is re- quired between these two pins to define the trip point. A re- sistor of around 910 K has been found to be the best value for startup operation. This resistor value will result in a start- up time of around 400 ms. Lower values will provide quicker startup times, but the XTALout amplitude will diminish as the resistor size goes down. During power–down conditions, XTALout is placed in a high–impedance state, and XTALin is internally discon- nected, so the device needs to be powered up in order to al- low the input of external signals or crystal usage. During normal operation, an external signal can be applied to XTALin, instead of a crystal. It should be noted that the phase of this signal and the internal signal (derived from XTALin) are inverted. The drive capability of XTALout is somewhat small, so it will be harder to start up the oscillation if the external resistor is too large (> 5 M Ω). The crystal value and/or external clock signal should be kept below 30 MHz. MCLK0 and MCLK1 Master Clock Inputs for Codec 0 and Codec 1 (Pins 5 and 6, Respectively) These pins are the master clock inputs for the codecs when the timing is not derived from the crystal. The master clock is equal to the oversampling clock. PDI Absolute Power–Down Input (Pin 7) This pin turns off any activity in the MC143416 except the power monitor function by stopping the oscillator. After any assertion of the PDI pin, a 10 ms period is required to resume functional operation. This time constraint is needed for the crystal oscillator to start up and stabilize to its defined operat- ing point. It is mandatory to apply a hardware reset after this oscillator startup phase. Alternatively, a software reset can be applied after this startup phase and after making sure the serial interface framing logic has synced up to the host con- trol/data frame. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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