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C7884-01 Datasheet(PDF) 2 Page - Hamamatsu Corporation |
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C7884-01 Datasheet(HTML) 2 Page - Hamamatsu Corporation |
2 / 6 page NMOS linear image sensor S3901/S3904 series s Shape specifications Parameter S3901-128Q S3901-256Q S3901-512Q S3904-256Q S3904-512Q S3904-1024Q Unit Number of pixels 128 256 512 256 512 1024 - Package length 31.75 40.6 31.75 40.6 mm Number of pins 22 22 - Window material*3 Quartz Quartz - Weight 3.0 3.5 3.0 3.5 g *3: Fiber optic plate is available (excluding the S3901-128Q, S3904-256Q). s Specifications (Ta=25 °C) S3901 series S3904 series Parameter Symbol Min. Typ. Max. Min. Typ. Max. Unit Pixel pitch - - 50 - - 25 - µm Pixel height - - 2.5 - - 2.5 - mm Spectral response range (10% of peak) λ 200 to 1000 200 to 1000 nm Peak sensitivity wavelength λp - 600 - - 600 - nm Photodiode dark current*4 ID - 0.2 0.6 - 0.1 0.3 pA Photodiode capacitance*4 Cph - 20 - - 10 - pF Saturation exposure*4 *5 Esat - 180 - - 180 - mlx · s Saturation output charge*4 Qsat - 50 - - 25 - pC Photo response non-uniformity*6 PRNU - - ±3 - - ±3 % *4: Vb=2.0 V, V φ=5.0 V *5: 2856 K, tungsten lamp *6: 50% of saturation, excluding the start pixel and last pixel s Electrical characteristics (Ta=25 °C) S3901 series S3904 series Parameter Symbol C ondition Min. Typ. Max. Min. Typ. Max. Unit High V φ1, Vφ2 (H) 4.5 5 10 4.5 5 10 V Clock pulse ( φ1, φ2) voltage Low V φ1, Vφ2 (L) 0 - 0.4 0 - 0.4 V High V φs (H) 4.5 V φ1 10 4.5 V φ1 10 V Start pulse ( φst) voltage Low V φs (L) 0 - 0.4 0 - 0.4 V Video bias voltage*7 Vb 1.5 V φ - 3.0 Vφ - 2.5 1.5 V φ - 3.0 Vφ - 2.5 V Saturation control gate voltage Vscg - 0 - - 0 - V Saturation control drain voltage Vscd - Vb - - Vb - V C lock pulse ( φ1, φ2) rise / fall tim e*8 tr φ1, trφ2 tf φ1, tfφ2 - 20 - - 20 - ns Clock pulse ( φ1, φ2) pulse width tpw φ1, tpwφ2 200 - - 200 - - ns Start pulse ( φst) rise / fall time tr φs, tfφs - 20 - - 20 - ns Start pulse ( φst) pulse width tpw φs 200 - - 200 - - ns Start pulse ( φst) and clock pulse ( φ2) overlap t φov 200 - - 200 - - ns Clock pulse space* 8 X1, X2 trf - 20 - - trf - 20 - - ns Data rate*9 f 0.1 - 2000 0.1 - 2000 kHz - 80 (-128 Q) - - 100 (-256 Q ) - ns - 120 (-256 Q) - - 150 (-512 Q ) - ns Video delay time tvd 50 % of s a tu ra tio n *9 *10 - 160 (-512 Q) - - 200 (-1024 Q ) - ns - 21 (-128 Q) - - 27 (-256 Q ) - pF - 36 (-256 Q) - - 50 (-512 Q ) - pF Clock pulse ( φ1, φ2) line capacitance C φ 5 V bias - 67 (-512 Q) - - 100 (-1024 Q ) - pF - 12 (-128 Q) - - 14 (-256 Q ) - pF - 20 (-256 Q) - - 24 (-512 Q ) - pF Saturation control gate (Vscg) line capacitance Cscg 5 V bias - 35 (-512 Q) - - 45 (-1024 Q ) - pF - 7 (-128 Q) - - 10 (-256 Q ) - pF - 11 (-256 Q) - - 16 (-512 Q ) - pF Video line capacitance CV 2 V bias - 20 (-512 Q) - - 30 (-1024 Q ) - pF *7: V φ is input pulse voltage (refer to “sVideo bias voltage m argin”). *8: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be input if the clock pulse rise or fall time is longer than 20 ns (refer to “sTim ing c hart fo r driv e r c irc uit”). *9: Vb=2.0 V, V φ=5.0 V *10: Measured with C7883 driver circuit. 2 |
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