NCP3020A, NCP3020B

http://onsemi.com

2

GATE

DRIVE

LOGIC

VC

CLK/

DMAX/

SOFT

START

OOV

BOOST

CLAMP

LEVEL

SHIFT

SAMPLE &

HOLD

VC

HSDR

LSDR

GND

−

+

−

+

−

+

VCC

COMP

FB

REF

RAMP

OSCILLATOR

BST

VSW

VCC

Figure 2. NCP3020 Block Diagram

INTERNAL BIAS

ISET

1.5 V

BST_CHRG

THERMAL SD

POR/STARTUP

OTA

PWM

COMP

OUV

CURRENT

LIMIT

PIN FUNCTION DESCRIPTION

Pin

Pin Name

Description

1

in the high side MOSFET.

2

COMP

The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive

terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage

mode control feedback loop.

3

FB

The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to

compensate the voltage mode control feedback loop.

4

GND

Ground Pin

5

LSDR

The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side

to GND.

6

VSW

current in the high side MOSFET.

7

HSDR

The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side

N−FET.

8

BST

The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the

VSW pin.