©1999 Fairchild Semiconductor Corporation

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74LVT373, 74LVTH373 Rev. 1.5.0

2

Connection Diagram

Pin Description

Functional Description

The LVT373 and LVTH373 contain eight D-type latches

with 3-STATE standard outputs. When the Latch Enable

latches. In this condition the latches are transparent, i.e.,

a latch output will change state each time its D input

changes. When LE is LOW, the latches store the infor-

mation that was present on the D inputs a setup time

preceding the HIGH-to-LOW transition of LE. The

3-STATE standard outputs are controlled by the Output

Enable (OE) input. When OE is LOW, the standard out-

puts are in the 2-state mode. When OE is HIGH, the

standard outputs are in the high impedance mode but

this does not interfere with entering new data into the

latches.

Logic Symbols

IEEE/IEC

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

Z

= High Impedance

X

= Immaterial

of Latch Enable

Pin Names

Description

Data Inputs

LE

Latch Enable Input

OE

Output Enable Input

3-STATE Latch Outputs

Inputs

Outputs

LE

OE

XHX

Z

HL

L

L

HLH

H

LL

X