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ADSP-BF527C Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-BF527C Datasheet(HTML) 8 Page - Analog Devices |
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8 / 44 page  Rev. PrC | Page 8 of 44 | June 2008 ADSP-BF523C/ADSP-BF525C/ADSP-BF527C Preliminary Technical Data inputs. These allow a matched interface to the multi-bit over- sampling ADC and prevent high frequencies from aliasing into the audio band to degrade performance. Software control for MICIN is shown in Table 2. The micro- phone mute only mutes the input to the ADC, which allows the microphone input signal to pass to the line output in sidetone mode. There are two stages of gain made up of two low noise inverting operational amplifiers. The first stage has a nominal gain of G1 = 50 kΩ/10 kΩ =5. The gain of the stage can be adjusted by adding an external resistor (Rmic) in series with MICIN (see Figure 6 on Page 9). The equa- tion below can be used to calculate the gain versus Rmic. Gain = 50 kΩ/(Rmic + 10 kΩ) Or to calculate the value of Rmic to achieve a given gain: Rmic = (50 kΩ/Gain)–10 kΩ For example adding Rmic =40kΩ sets the gain of stage one to 1x (0 dB). For Rmic = 90 kΩ gain = 0.5 (–6 dB) and for Rmic = 0 gain = 5x (14 dB). The internal 50 kΩ and 10 kΩ resistors have a tolerance of 15%. The second stage has 0 dB gain that can be software configured to provide a fixed 20 dB of gain for low sensitivity microphones. The microphone input can therefore be configured with a vari- able gain of between –6 dB and 14 dB on the first stage, and an additional fixed 0 dB or 20 dB on the second stage. This allows a total gain of –6 dB to 34 dB. To maximize the signal-to-noise ratio, stage 1 and stage 2 gains should be configured so that the maximum signal that the ADC receives is equal to the full scale value. The ADC full scale input is 1.0 V(rms) at AVDD = 3.3 volts. Any voltage greater than full scale could overload the ADC and cause distortion. The full scale input tracks directly with AVDD. The microphone input is biased internally through the opera- tional amplifier to VMID. Whenever the line inputs are muted the MICIN input is kept biased to VMID using special anti- thump circuitry. This reduces audible clicks that may otherwise be heard when re-activating the input. Table 1. Line Input Software Control Register Address Bit Label Default Description 000 0000 Left Line In 4:0 LINVOL[4:0] 10111 ( 0 dB ) Left Channel Line Input Volume Control 11111 = +12 dB in 1.5 dB steps down to 00000 = –34.5 dB 7 LINMUTE 1 Left Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 8 LRINBOTH 0 Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load 000 0001 Right Line In 4:0 RINVOL[4:0] 10111 ( 0 dB ) Right Channel Line Input Volume Control 11111 = +12 dB in 1.5 dB steps down to 00000 = –34.5 dB 7 RINMUTE 1 Right Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 8 RLINBOTH 0 Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load Figure 5. Microphone Input Internal Circuit Table 2. Microphone Input Software Control Register Address Bit Label Default Description 000 0100 0 MICBOOST 0 Microphone Input Level Boost 1 = Enable Boost 0 = Disable Boost 1 MUTEMIC 1 Microphone Mute to ADC 1 = Enable Mute 0 = Disable Mute TO ADC + - + - MICIN 10 K 50 K VMID VMID |
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