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SI2705-A10-GM Datasheet(PDF) 9 Page - Silicon Laboratories |
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SI2705-A10-GM Datasheet(HTML) 9 Page - Silicon Laboratories |
9 / 46 page Si2704/05/06/07-A10 Rev. 0.6 9 Figure 1. Digital Audio Timing Parameters Table 8. 2-Wire Control Interface Characteristics (VIO = 1.62 to 3.6 V, TA = –20 to +85 °C, unless otherwise noted). Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0— 400 kHz SCLK Low Time tLOW 1.3 — — µs SCLK High Time tHIGH 0.6 — — µs SCLK Input from SDIO Setup ↓ (START) tSU:STA 0.6 — — µs SCLK Input to SDIO ↓ Hold (START) tHD:STA 0.6 — — µs SDIO Input to SCLK ↑ Setup tSU:DAT 100 — — ns SDIO Input to SCLK ↓ Hold tHD:DAT 0— 900 ns SDIO output delay TPD:DAT 300 — 900 ns SCLK input to SDIO ↑ Setup (STOP) tSU:STO 0.6 — — µs STOP to START Time tBUF 1.3 — — µs SDIO Output Fall Time tf:OUT —— 250 ns SDIO Input, SCLK Rise/Fall Time tf:IN tr:IN —— 300 ns Capacitive Loading Cb —— 50 pF Pulse Width Rejected by Input Filter tSP —— 50 ns |
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