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SI2706-A10-GQ Datasheet(PDF) 8 Page - Silicon Laboratories |
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SI2706-A10-GQ Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 46 page Si2704/05/06/07-A10 8 Rev. 0.6 Power Supply Rejection Ratio PSRR PO = –3 dBFS, f = 1 kHz; 200 mVPP, fr = 400 Hz supply ripple —50 — dB Crosstalk f = 1 kHz — –92 — dB Efficiency4 η f = 1 kHz, half rate PWM and 10 ns slew rate —88 — % Output Pulse Repetition Frequency PRF Half Rate PWM — 480 — kHz Full Rate PWM — 960 — kHz Table 6. AC Characteristics—PWM Digital to Analog Converter (VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, VOL = 0 dBFS, TA = -20 to +85 °C, unless otherwise noted). Parameter Symbol Test Condition Min Typ Max Unit Total Harmonic Distortion + Noise THD+N f = 1 kHz — 0.02 — % Signal to Noise Ratio/Dynamic Range SNR f = 1 kHz, A-weighted — 88 — dB f = 1 kHz, Unweighted — 85 — dB Output Voltage Swing Vout — 1 — VP-P Output Voltage Common Mode Bias Voutcm — 0.8 — V Output Load— Resistance Rload AC coupled 5 — 50 k Ω Output Load— Capacitance Cload AC coupling capacitor 0.1 — 1 µF Table 7. I2S Digital Audio Interface Characteristics (VIO = 1.62 to 3.6 V, TA = –20 to +85 °C, unless otherwise noted). Parameter Symbol Test Condition Min Typ Max Unit DCLK Input Cycle Time tCYC:DCLK 70 — — ns DCLK Input Pulse Width High tHI:DCLK 0.4 x tCYC:DCLK —0.6 x tCYC:DCLK ns DCLK Input Pulse Width Low tLO:DCLK 0.4 x tCYC:DCLK —0.6 x tCYC:DCLK ns DFS Setup Time to DCLK ↑ tSU:DCLK 10 — — ns DFS Hold Time after DCLK ↑ tHD:DCLK 5— — ns DOUT Output Delay TPD:DCLK 0— 35 ns Capacitive Loading CB — — 15 pF Table 5. AC Characteristics—Class D Amplifier (Continued) (VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, VPP = 6.6 V, RL = 8 Ω, VOL = 0 dBFS, TA = –20 to +85 °C, unless otherwise noted.) Notes: 1. Measured at filter output. Power measured at the chip output is greater. 2. Guaranteed by characterization. 3. Measured relative to the integrated noise floor in Spread mode. Guaranteed by characterization. 4. Does not include filter efficiency losses. |
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