Electronic Components Datasheet Search |
|
TLE7273-2GV50 Datasheet(PDF) 5 Page - Infineon Technologies AG |
|
TLE7273-2GV50 Datasheet(HTML) 5 Page - Infineon Technologies AG |
5 / 26 page Data Sheet 5 Rev. 1.2, 2009-04-28 TLE7273-2 Pin Configuration 3.3 Pin Assignments (PG-SSOP-14 Exposed Pad) Figure 3 Pin Assignment PG-SSOP-14 Exposed Pad (top view) 3.4 Pin Definitions and Functions (PG-SSOP-14 Exposed Pad) Table 2 Pin Definitions and Functions Pin No. Symbol Function 1 RO Reset Output integrated 20 k Ω pull-up resistor (TLE7273-2EV50); leave open if not needed 2, 5 GND Ground connect to GND 3, 4, 10, 11, 12 n.c. not connected leave open or connect to GND 6 WM2 Watchdog Mode Bit 2 watchdog and reset mode selection, see Figure 5; connect to V Q or GND 7 WM1 Watchdog Mode Bit 1 watchdog and reset mode selection, see Figure 5; connect to V Q or GND 8 WDI Watchdog Input trigger input for watchdog pulses; pull down to GND if not needed and turn off the watchdog with WM1 and WM2 pin 9 Q Output Voltage block to GND with a ceramic capacitor C Q ≥ 470 nF close to IC terminal 13 I Input Voltage block to ground directly at the IC with a 100 nF ceramic capacitor 14 EN Enable Input low level disables the IC; integrated pull-down resistor Pad – Exposed Pad connect to heatsink area; connect with GND on PCB |
Similar Part No. - TLE7273-2GV50 |
|
Similar Description - TLE7273-2GV50 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |