______________________________________________________________________________________ 11

14-/16-Bit, Low-Power,

High-Performance, Buffered Single DACs

Pin Description

Pin Configuration

Detailed Description

The MAX5214/MAX5216 are pin-compatible and soft-

ware-compatible 14-bit and 16-bit DACs. The MAX5214/

MAX5216 are single-channel, low-power, high-refer-

ence input resistance, and buffered voltage-output

DACs. The MAX5214/MAX5216 minimize the digital

noise feedthrough from their inputs to their outputs by

powering down the SCLK and DIN input buffers after

completion of each data frame. The data frames are

16-bit for the MAX5214 and 24-bit for the MAX5216. On

power-up, the MAX5214/MAX5216 reset the DAC output

to zero, providing additional safety for applications that

drive valves or other transducers which need to be off on

power-up. The MAX5214/MAX5216 contain a segmented

resistor string-type DAC, a serial-in/parallel-out shift reg-

ister, a DAC register, power-on-reset (POR) circuit, CLR

to asynchronously clear the device independent of the

serial interface, and control logic. On the falling edge

of the clock (SCLK) pulse, the serial input (DIN) data is

shifted into the device, MSB first.

Output Amplifier (OUT)

The MAX5214/MAX5216 include an internal buffer on the

DAC output. The internal buffer provides improved load

regulation and transition glitch suppression for the DAC

output. The output buffer slews at 0.5V/Fs and drives

up to 10kI in parallel with 100pF. The analog supply

DAC Reference (REF)

The external reference input features a typical input

impedance of 256kI and accepts an input voltage

between REF and GND to apply an external reference.

of available voltage-reference devices.

OUT

CLR

DIN

1

2

8

7

GND

CS

SCLK

REF

µMAX

TOP VIEW

3

4

6

5

MAX5214

MAX5216

PIN

NAME

FUNCTION

1

REF

Reference Voltage Input. Bypass REF with a 0.1FF capacitor to GND.

2

CS

Active-Low Chip-Select Input

3

SCLK

Serial-Clock Input

4

DIN

Data In

5

CLR

Active-Low Asynchronous Digital-Clear Input. Drive CLR low to clear the contents of the input and

DAC registers and set the DAC output to zero.

6

OUT

Buffered DAC Output

7

8

GND

Ground