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MAX9205EAI Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX9205EAI Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 13 page Applications Information Power-Supply Bypassing Bypass AVCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to AVCC. Bypass DVCC with high-fre- quency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possi- ble, with the smaller valued capacitor closest to DVCC. Differential Traces and Termination Output trace characteristics affect the performance of the MAX9205/MAX9207. Use controlled-impedance media and terminate at both ends of the transmission line in the media's characteristic impedance. Termination with a single resistor at the end of a point- to-point link typically provides acceptable performance. However, the MAX9205/MAX9207 output levels are specified for double-terminated point-to-point and mul- tipoint applications. With a single 100 Ω termination, the output swing is larger. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. The differential output signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to fur- ther prevent impedance discontinuities. 10-Bit Bus LVDS Serializers _______________________________________________________________________________________ 7 OUT+ OUT- VOD VOS RL 2 RL 2 Figure 1. Output Voltage Definitions TCLK ODD IN_ EVEN IN_ TCLK_R/F = LOW Figure 2. Worst-Case ICC Test Pattern TCLK tCLKT 10% 90% 90% 10% tCLKT 0 3V Figure 3. Input Clock Transition Time Requirement |
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