Networking Silicon — 82562EP

Datasheet

3

2.0

82562EP Architectural Overview

The 82562EP is a highly integrated Platform LAN Connect device that combines 10BASE-T and

100BASE-TX physical layer interfaces. The 82562EP supports a single interface fully compliant

with the IEEE 802.3 standard. Figure 1 shows a block diagram of the 82562EP architecture.

Figure 1. 82562EP PLC Block Diagram

2.1

LAN Connect Interface

The 82562EP supports a LAN Connect Interface (LCI) as specified in the LCI Specification. The

LAN Connect is the I/O Control Hub 2 (ICH2) interface to the 82562EP. The LCI uses an 8-pin

interface, which reduces the pin count from 15, for an Media Independent Interface (MII) PHY. In

addition, its signaling protocol provides greater functionality, such as dynamic power reduction,

from a PLC in comparison to a standard MII PHY.

Figure 2 shows how the 82562EP can be used in a 10/100 Mbps ICHx design.

Figure 2. 82562EP PLC 10/100 Mbps Ethernet Solution

Equalizer &

BLW correction

CRS/Link 10

Detection

Digital Clock

Recovery (100)

Digital Clock

Recovery (10)

Digital

Equalizer

Adaptation

100Base-TX

PCS

Transmit DAC

10/100

Clock

Generator

RDN/RDP

TDN/TDP

LAN

Connect

Interface

Port LED

Drivers

LILED#

ACTLED#

SPDLED#

Auto-

Negotiation

Control

Registers

10Base-T

PCS

3

3

LAN_RSTSYNC

LAN_TXD[2:0]

LAN_RXD[2:0]

LAN_CLK

Bias & Band-

Gap Voltage

Circuit

X2

X1

Crystal

25 MHz

I/O Control Hub 4

(ICH4) LAN

Controller

82562EZ

(Platform LAN

Connect

Device)

Transmit Differential Pair

(TDP/TDN)

Receive Differential Pair

(RDP/RDN)

System Bus Interface

Magnetics

I/O Control Hub

LAN Controller

82562EP

PLC